Consider all sizes to be in bits instead
This commit is contained in:
parent
83e77c93bf
commit
09d598f1ff
@ -62,6 +62,7 @@ typedef uint32_t ArchOperand;
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/* flags */
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# define AOF_FILTER 0x1
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# define AOF_IMPLICIT 0x1 /* for registers */
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# define AOF_SIGNED 0x2 /* for immediate */
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# define AOF_SOFFSET 0x3
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@ -75,9 +76,9 @@ typedef uint32_t ArchOperand;
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# define AO_IMMEDIATE(flags, offset, size) ((AOT_IMMEDIATE << AOD_TYPE) \
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| (flags << AOD_FLAGS) | (offset << AOD_OFFSET) \
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| (size << AOD_SIZE))
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# define AO_REGISTER(flags, offset, size) ((AOT_REGISTER << AOD_TYPE) \
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# define AO_REGISTER(flags, offset, size, id) ((AOT_REGISTER << AOD_TYPE) \
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| (flags << AOD_FLAGS) | (offset << AOD_OFFSET) \
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| (size << AOD_SIZE))
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| (size << AOD_SIZE) | (id << AOD_VALUE))
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# define AO_DREGISTER(flags, offset, dsize) ((AOT_DREGISTER << AOD_TYPE) \
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| (flags << AOD_FLAGS) | (offset << AOD_OFFSET) \
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| (dsize << AOD_SIZE))
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36
src/arch.c
36
src/arch.c
@ -163,8 +163,8 @@ ArchInstruction * arch_get_instruction_by_opcode(Arch * arch, uint8_t size,
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/* arch_get_instruction_by_operands */
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static int _operands_operands(ArchInstruction * ai, AsOperand ** operands,
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size_t operands_cnt);
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static int _operands_operands(Arch * arch, ArchInstruction * ai,
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AsOperand ** operands, size_t operands_cnt);
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ArchInstruction * arch_get_instruction_by_operands(Arch * arch,
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char const * name, AsOperand ** operands, size_t operands_cnt)
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@ -183,7 +183,7 @@ ArchInstruction * arch_get_instruction_by_operands(Arch * arch,
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if(strcmp(ai->name, name) != 0)
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continue;
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found = 1;
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if(_operands_operands(ai, operands, operands_cnt) == 0)
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if(_operands_operands(arch, ai, operands, operands_cnt) == 0)
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return ai;
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}
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error_set_code(1, "%s \"%s\"", found ? "Invalid arguments to"
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@ -191,11 +191,12 @@ ArchInstruction * arch_get_instruction_by_operands(Arch * arch,
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return NULL;
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}
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static int _operands_operands(ArchInstruction * ai, AsOperand ** operands,
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size_t operands_cnt)
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static int _operands_operands(Arch * arch, ArchInstruction * ai,
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AsOperand ** operands, size_t operands_cnt)
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{
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size_t i;
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uint32_t operand;
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ArchRegister * ar;
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for(i = 0; i < operands_cnt; i++)
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{
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@ -203,12 +204,30 @@ static int _operands_operands(ArchInstruction * ai, AsOperand ** operands,
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return -1;
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operand = (i == 0) ? ai->op1 : ((i == 1) ? ai->op2 : ai->op3);
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#ifdef DEBUG
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fprintf(stderr, "DEBUG: %s() %lu %u, %u\n", __func__, i,
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AO_GET_TYPE(operand),
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fprintf(stderr, "DEBUG: %s() operand %lu, type %u, type %u\n",
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__func__, i, AO_GET_TYPE(operand),
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AO_GET_TYPE(operands[i]->operand));
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#endif
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if(AO_GET_TYPE(operand) != AO_GET_TYPE(operands[i]->operand))
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return -1;
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switch(AO_GET_TYPE(operand))
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{
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case AOT_REGISTER:
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/* check if it exists */
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ar = arch_get_register_by_name(arch,
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operands[i]->value);
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if(ar == NULL)
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return -1;
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/* for implicit instructions it must match */
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if(AO_GET_FLAGS(operand) & AOF_IMPLICIT)
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{
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if(AO_GET_SIZE(operand) != ar->size)
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return -1;
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if(AO_GET_VALUE(operand) != ar->id)
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return -1;
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}
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break;
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}
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/* FIXME check AOF_SIGNED */
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}
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return 0;
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@ -248,6 +267,9 @@ ArchRegister * arch_get_register_by_name(Arch * arch, char const * name)
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{
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size_t i;
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#ifdef DEBUG
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fprintf(stderr, "DEBUG: %s(\"%s\")\n", __func__, name);
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#endif
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for(i = 0; i < arch->registers_cnt; i++)
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if(strcmp(arch->plugin->registers[i].name, name) == 0)
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return &arch->plugin->registers[i];
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@ -21,6 +21,24 @@
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/* i386 */
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/* private */
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/* types */
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/* register sizes */
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#define REG(name, size, id) REG_ ## name ## _size = size,
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enum
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{
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#include "i386.reg"
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};
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#undef REG
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/* register ids */
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#define REG(name, size, id) REG_ ## name ## _id = id,
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enum
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{
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#include "i386.reg"
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};
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#undef REG
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/* variables */
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#define REG(name, size, id) { "" # name, size, id },
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static ArchRegister _i386_registers[] =
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@ -28,6 +46,7 @@ static ArchRegister _i386_registers[] =
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#include "i386.reg"
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{ NULL, 0, 0 }
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};
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#undef REG
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static ArchInstruction _i386_instructions[] =
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{
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@ -1,9 +1,28 @@
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/* platform-specific */
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#if defined(ARCH_amd64)
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# define W 32
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#elif defined(ARCH_i386_real)
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# define W 16
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#else /* i386 and compatible */
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# define W 32
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#endif
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/* registers */
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#define OP_al AO_REGISTER(AOF_IMPLICIT, 0, REG_al_size, REG_al_id)
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#define OP_AX AO_REGISTER(AOF_IMPLICIT, 0, W, REG_ax_id)
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/* helpers */
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#define OP1F (1 << AOD_SIZE)
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#define OP2F (2 << AOD_SIZE)
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#define OP_U8 AO_IMMEDIATE(0, 0, 1)
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#define OP_U8 AO_IMMEDIATE(0, 0, 8)
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#define OP_UW AO_IMMEDIATE(0, 0, W)
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{ "aaa", 0x37, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "aad", 0xd5a0, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "aad", 0xd50a, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "aad", 0xd5, OP1F, OP_U8, AOT_NONE, AOT_NONE },
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{ "aam", 0xd40a, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "aam", 0xd4, OP1F, OP_U8, AOT_NONE, AOT_NONE },
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{ "aas", 0x3f, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "adc", 0x14, OP1F, OP_U8, OP_al, AOT_NONE },
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{ "adc", 0x15, OP1F, OP_UW, OP_AX, AOT_NONE },
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{ "nop", 0x90, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
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@ -1,40 +1,40 @@
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REG(ah, 8, 0x00)
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REG(al, 8, 0x01)
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REG(bh, 8, 0x02)
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REG(bl, 8, 0x03)
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REG(ch, 8, 0x04)
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REG(cl, 8, 0x05)
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REG(dh, 8, 0x06)
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REG(dl, 8, 0x07)
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REG(ax, 16, 0x00)
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REG(ah, 8, 0x01)
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REG(al, 8, 0x02)
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REG(bx, 16, 0x03)
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REG(bh, 8, 0x04)
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REG(bl, 8, 0x05)
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REG(cx, 16, 0x06)
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REG(ch, 8, 0x07)
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REG(cl, 8, 0x08)
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REG(dx, 16, 0x09)
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REG(dh, 8, 0x0a)
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REG(dl, 8, 0x0b)
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REG(sp, 16, 0x0c)
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REG(bp, 16, 0x0d)
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REG(si, 16, 0x0e)
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REG(di, 16, 0x0f)
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REG(cs, 16, 0x10)
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REG(ss, 16, 0x11)
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REG(ds, 16, 0x12)
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REG(es, 16, 0x13)
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REG(fs, 16, 0x14)
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REG(gs, 16, 0x15)
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REG(bx, 16, 0x01)
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REG(cx, 16, 0x02)
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REG(dx, 16, 0x03)
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REG(sp, 16, 0x04)
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REG(bp, 16, 0x05)
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REG(si, 16, 0x06)
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REG(di, 16, 0x07)
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REG(cs, 16, 0x08)
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REG(ss, 16, 0x09)
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REG(ds, 16, 0x0a)
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REG(es, 16, 0x0b)
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REG(fs, 16, 0x0c)
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REG(gs, 16, 0x0d)
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#ifndef ARCH_i386_real
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REG(eax,32, 0x16)
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REG(ebx,32, 0x17)
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REG(ecx,32, 0x18)
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REG(edx,32, 0x19)
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REG(esi,32, 0x1a)
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REG(edi,32, 0x1b)
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REG(esp,32, 0x1c)
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REG(ebp,32, 0x1d)
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REG(eax,32, 0x00)
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REG(ebx,32, 0x01)
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REG(ecx,32, 0x02)
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REG(edx,32, 0x03)
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REG(esi,32, 0x04)
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REG(edi,32, 0x05)
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REG(esp,32, 0x06)
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REG(ebp,32, 0x07)
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#endif /* !ARCH_i386_real */
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REG(st0,32, 0x1f)
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REG(st1,32, 0x20)
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REG(st2,32, 0x21)
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REG(st3,32, 0x22)
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REG(st4,32, 0x23)
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REG(st5,32, 0x24)
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REG(st6,32, 0x25)
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REG(st7,32, 0x26)
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REG(st0,32, 0x08)
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REG(st1,32, 0x09)
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REG(st2,32, 0x0a)
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REG(st3,32, 0x0b)
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REG(st4,32, 0x0c)
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REG(st5,32, 0x0d)
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REG(st6,32, 0x0e)
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REG(st7,32, 0x0f)
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@ -1,7 +1,7 @@
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/* $Id$ */
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/* generic */
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/* registers */
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#define OP_RD AO_REGISTER(0, 25, 5)
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#define OP_RD AO_REGISTER(0, 25, 5, 0)
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/* conditional branching */
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/* opcodes */
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@ -57,8 +57,8 @@
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#define OPIA1F (4 << AOD_SIZE)
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#define OPIA2F (4 << AOD_SIZE)
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/* registers */
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#define OPIA_RS1 AO_REGISTER(0, 14, 5)
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#define OPIA_RS2 AO_REGISTER(0, 0, 5)
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#define OPIA_RS1 AO_REGISTER(0, 14, 5, 0)
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#define OPIA_RS2 AO_REGISTER(0, 0, 5, 0)
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/* helpers */
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#define OPIA1(opcode) (0x80000000 | opcode << 19)
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#define OPIA2(opcode) (0x80000000 | opcode << 19 | 0x1 << 13)
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71
src/code.c
71
src/code.c
@ -190,6 +190,8 @@ static int _instruction_variable_immediate(Code * code, ArchOperand operand,
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static int _instruction_variable_opcode(Code * code, ArchInstruction * ai);
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static int _instruction_variable_operand(Code * code, ArchInstruction * ai,
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ArchOperand operand, AsOperand * aso);
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static int _instruction_variable_register(Code * code, ArchOperand operand,
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char const * name);
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int code_instruction(Code * code, char const * name, AsOperand ** operands,
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size_t operands_cnt)
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@ -326,33 +328,38 @@ static int _instruction_variable_immediate(Code * code, ArchOperand operand,
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#ifdef DEBUG
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fprintf(stderr, "DEBUG: %s()\n", __func__);
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#endif
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switch((size = AO_GET_SIZE(operand)))
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if((size = AO_GET_SIZE(operand)) == 0)
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return -error_set_code("%s", "Empty immediate value");
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else if(size <= 8)
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{
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case 0:
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break;
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case sizeof(u8):
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u8 = *(uint8_t*)value;
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buf = &u8;
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break;
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case sizeof(u16):
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u16 = *(uint16_t*)value;
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u16 = htons(u16);
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buf = &u16;
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break;
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case 3: /* XXX check */
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u32 = *(uint32_t*)value;
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u32 = htonl(u32 << 8);
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buf = &u32;
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break;
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case sizeof(u32):
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u32 = *(uint32_t*)value;
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u32 = htonl(u32);
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buf = &u32;
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break;
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default:
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return -1; /* XXX return error */
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u8 = *(uint8_t*)value;
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buf = &u8;
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size = 1;
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}
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if(size > 0 && fwrite(buf, size, 1, code->fp) != 1)
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else if(size <= 16)
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{
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u16 = *(uint16_t*)value;
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u16 = htons(u16);
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buf = &u16;
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size = 2;
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}
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else if(size <= 24) /* FIXME merge with 32 */
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{
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u32 = *(uint32_t*)value;
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u32 = htonl(u32 << 8);
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buf = &u32;
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size = 3;
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}
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else if(size <= 32)
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{
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u32 = *(uint32_t*)value;
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u32 = htonl(u32);
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buf = &u32;
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size = 4;
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}
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else
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return -error_set_code(1, "%u: Size not implemented", size);
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if(fwrite(buf, size, 1, code->fp) != 1)
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return -error_set_code(1, "%s: %s", code->filename, strerror(
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errno));
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return 0;
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@ -371,12 +378,24 @@ static int _instruction_variable_operand(Code * code, ArchInstruction * ai,
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case AOT_IMMEDIATE:
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return _instruction_variable_immediate(code, operand,
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aso->value);
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case AOT_REGISTER:
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return _instruction_variable_register(code, operand,
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aso->value);
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default:
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/* FIXME implement */
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return -1;
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return -error_set_code(1, "%s", strerror(ENOSYS));
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}
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return 0;
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}
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static int _instruction_variable_register(Code * code, ArchOperand operand,
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char const * name)
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{
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if(AO_GET_FLAGS(operand) & AOF_IMPLICIT)
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return 0;
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/* FIXME implement */
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return -error_set_code(1, "%s: %s", name, strerror(ENOSYS));
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}
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#if 0
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switch(AO_GET_SIZE(ai->opcode))
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{
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@ -555,7 +555,7 @@ static int _operand(State * state)
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0, 0);
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else
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(*p)->operand = AO_REGISTER(0,
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0, 0);
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0, 0, 0);
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/* FIXME check errors */
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(*p)->value = strdup(string);
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break;
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@ -2,4 +2,9 @@
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aaa
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aad
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aad $0x42
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aam
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aam $0x42
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aas
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adc $0x42, %al
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adc $0x42, %eax
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nop
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