Improving ARM support
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@ -39,6 +39,11 @@ static int _arm_write(ArchPlugin * plugin, ArchInstruction * instruction,
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switch(instruction->opcode & 0x0fffffff) /* ignore condition code */
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{
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/* branch, branch with link */
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case OPB(0):
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case OPBL(0):
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opcode |= call->operands[0].value.immediate.value;
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break;
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/* branch and exchange */
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case OPBX(0):
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/* first operand, Rn */
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@ -195,6 +200,23 @@ static int _arm_write(ArchPlugin * plugin, ArchInstruction * instruction,
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/* second operand */
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opcode |= call->operands[1].value.immediate.value;
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break;
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/* psr transfer */
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case OPPT(0):
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/* first operand, Rd */
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p = call->operands[0].value._register.name;
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if((ar = helper->get_register_by_name_size(helper->arch,
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p, 32)) == NULL)
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return -1;
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opcode |= (ar->id << 12);
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break;
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case OPPTI(0):
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/* second operand, Rm */
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p = call->operands[1].value._register.name;
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if((ar = helper->get_register_by_name_size(helper->arch,
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p, 32)) == NULL)
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return -1;
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opcode |= ar->id;
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break;
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#if 1 /* FIXME really implement */
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default:
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break;
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14
test/arm.S
14
test/arm.S
@ -81,13 +81,13 @@
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mrc %r0, %r0, %r0
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mrceq %r0, %r0, %r0
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mrs %r0, %cpsr
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mrseq %r0, %cpsr
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mrs %r0, %spsr
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mrseq %r0, %spsr
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msr %cpsr, %r0
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msreq %cpsr, %r1
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msr %spsr, %r0
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msreq %spsr, %r1
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mrseq %r1, %cpsr
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mrs %r2, %spsr
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mrseq %r3, %spsr
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msr %cpsr, %r4
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msreq %cpsr, %r5
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msr %spsr, %r6
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msreq %spsr, %r7
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mul %r0, %r1, %r2
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muls %r0, %r1, %r2
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mvn %r5, %r4
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