Code cleanup
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b2120b5582
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281dd9d9c4
129
src/arch/arm.h
129
src/arch/arm.h
@ -39,26 +39,27 @@ static int _arm_write(ArchPlugin * plugin, ArchInstruction * instruction,
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switch(instruction->opcode & 0x0fffffff) /* ignore condition code */
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{
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case and:
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case eor:
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case sub:
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case rsb:
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case add:
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case adc:
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case sbc:
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case rsc:
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case orr:
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case bic:
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case and | (0x1 << 20): /* ands */
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case eor | (0x1 << 20): /* eors */
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case sub | (0x1 << 20): /* subs */
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case rsb | (0x1 << 20): /* rsbs */
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case add | (0x1 << 20): /* adds */
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case adc | (0x1 << 20): /* adcs */
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case sbc | (0x1 << 20): /* sbcs */
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case rsc | (0x1 << 20): /* rscs */
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case orr | (0x1 << 20): /* orrs */
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case bic | (0x1 << 20): /* bics */
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/* data processing */
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case OPDP(0, and):
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case OPDP(0, eor):
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case OPDP(0, sub):
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case OPDP(0, rsb):
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case OPDP(0, add):
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case OPDP(0, adc):
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case OPDP(0, sbc):
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case OPDP(0, rsc):
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case OPDP(0, orr):
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case OPDP(0, bic):
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case OPDPS(0, and): /* ands */
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case OPDPS(0, eor): /* eors */
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case OPDPS(0, sub): /* subs */
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case OPDPS(0, rsb): /* rsbs */
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case OPDPS(0, add): /* adds */
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case OPDPS(0, adc): /* adcs */
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case OPDPS(0, sbc): /* sbcs */
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case OPDPS(0, rsc): /* rscs */
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case OPDPS(0, orr): /* orrs */
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case OPDPS(0, bic): /* bics */
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/* first operand, Rd */
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p = call->operands[0].value._register.name;
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if((ar = helper->get_register_by_name_size(helper->arch,
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@ -78,26 +79,26 @@ static int _arm_write(ArchPlugin * plugin, ArchInstruction * instruction,
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return -1;
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opcode |= ar->id;
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break;
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case and | (0x1 << 25):
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case eor | (0x1 << 25):
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case sub | (0x1 << 25):
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case rsb | (0x1 << 25):
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case add | (0x1 << 25):
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case adc | (0x1 << 25):
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case sbc | (0x1 << 25):
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case rsc | (0x1 << 25):
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case orr | (0x1 << 25):
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case bic | (0x1 << 25):
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case and | (0x1 << 25) | (0x1 << 20): /* ands (immediate) */
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case eor | (0x1 << 25) | (0x1 << 20): /* eors (immediate) */
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case sub | (0x1 << 25) | (0x1 << 20): /* subs (immediate) */
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case rsb | (0x1 << 25) | (0x1 << 20): /* rsbs (immediate) */
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case add | (0x1 << 25) | (0x1 << 20): /* adds (immediate) */
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case adc | (0x1 << 25) | (0x1 << 20): /* adcs (immediate) */
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case sbc | (0x1 << 25) | (0x1 << 20): /* sbcs (immediate) */
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case rsc | (0x1 << 25) | (0x1 << 20): /* rscs (immediate) */
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case orr | (0x1 << 25) | (0x1 << 20): /* orrs (immediate) */
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case bic | (0x1 << 25) | (0x1 << 20): /* bics (immediate) */
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case OPDPI(0, and):
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case OPDPI(0, eor):
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case OPDPI(0, sub):
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case OPDPI(0, rsb):
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case OPDPI(0, add):
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case OPDPI(0, adc):
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case OPDPI(0, sbc):
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case OPDPI(0, rsc):
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case OPDPI(0, orr):
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case OPDPI(0, bic):
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case OPDPIS(0, and): /* ands (immediate) */
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case OPDPIS(0, eor): /* eors (immediate) */
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case OPDPIS(0, sub): /* subs (immediate) */
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case OPDPIS(0, rsb): /* rsbs (immediate) */
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case OPDPIS(0, add): /* adds (immediate) */
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case OPDPIS(0, adc): /* adcs (immediate) */
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case OPDPIS(0, sbc): /* sbcs (immediate) */
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case OPDPIS(0, rsc): /* rscs (immediate) */
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case OPDPIS(0, orr): /* orrs (immediate) */
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case OPDPIS(0, bic): /* bics (immediate) */
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/* first operand, Rd */
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p = call->operands[0].value._register.name;
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if((ar = helper->get_register_by_name_size(helper->arch,
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@ -113,14 +114,14 @@ static int _arm_write(ArchPlugin * plugin, ArchInstruction * instruction,
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/* third operand */
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opcode |= call->operands[2].value.immediate.value;
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break;
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case tst:
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case teq:
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case cmp:
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case cmn:
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case tst | (0x1 << 20): /* tsts */
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case teq | (0x1 << 20): /* teqs */
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case cmp | (0x1 << 20): /* cmps */
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case cmn | (0x1 << 20): /* cmns */
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case OPDP(0, tst):
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case OPDP(0, teq):
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case OPDP(0, cmp):
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case OPDP(0, cmn):
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case OPDPS(0, tst): /* tsts */
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case OPDPS(0, teq): /* teqs */
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case OPDPS(0, cmp): /* cmps */
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case OPDPS(0, cmn): /* cmns */
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/* first operand, Rn */
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p = call->operands[0].value._register.name;
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if((ar = helper->get_register_by_name_size(helper->arch,
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@ -134,14 +135,14 @@ static int _arm_write(ArchPlugin * plugin, ArchInstruction * instruction,
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return -1;
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opcode |= ar->id;
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break;
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case tst | (0x1 << 25):
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case teq | (0x1 << 25):
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case cmp | (0x1 << 25):
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case cmn | (0x1 << 25):
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case tst | (0x1 << 25) | (0x1 << 20): /* tsts (immediate) */
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case teq | (0x1 << 25) | (0x1 << 20): /* teqs (immediate) */
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case cmp | (0x1 << 25) | (0x1 << 20): /* cmps (immediate) */
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case cmn | (0x1 << 25) | (0x1 << 20): /* cmns (immediate) */
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case OPDPI(0, tst):
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case OPDPI(0, teq):
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case OPDPI(0, cmp):
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case OPDPI(0, cmn):
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case OPDPIS(0, tst): /* tsts (immediate) */
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case OPDPIS(0, teq): /* teqs (immediate) */
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case OPDPIS(0, cmp): /* cmps (immediate) */
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case OPDPIS(0, cmn): /* cmns (immediate) */
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/* first operand, Rn */
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p = call->operands[0].value._register.name;
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if((ar = helper->get_register_by_name_size(helper->arch,
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@ -151,10 +152,10 @@ static int _arm_write(ArchPlugin * plugin, ArchInstruction * instruction,
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/* second operand */
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opcode |= call->operands[1].value.immediate.value;
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break;
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case mov:
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case mov | (0x1 << 20): /* movs */
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case mvn:
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case mvn | (0x1 << 20): /* mvns */
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case OPDP(0, mov):
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case OPDPS(0, mov): /* movs */
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case OPDP(0, mvn):
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case OPDPS(0, mvn): /* mvns */
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if(call->operands_cnt == 0) /* nop */
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break;
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/* first operand, Rd */
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@ -170,10 +171,10 @@ static int _arm_write(ArchPlugin * plugin, ArchInstruction * instruction,
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return -1;
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opcode |= ar->id;
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break;
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case mov | (0x1 << 25): /* mov (immediate) */
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case mov | (0x1 << 25) | (0x1 << 20): /* movs (immediate) */
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case mvn | (0x1 << 25): /* mvn (immediate) */
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case mvn | (0x1 << 25) | (0x1 << 20): /* mvns (immediate) */
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case OPDPI(0, mov): /* mov (immediate) */
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case OPDPIS(0, mov): /* movs (immediate) */
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case OPDPI(0, mvn): /* mvn (immediate) */
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case OPDPIS(0, mvn): /* mvns (immediate) */
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if(call->operands_cnt == 0) /* nop */
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break;
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/* first operand, Rd */
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