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Improving ARM support

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This commit is contained in:
Pierre Pronchery 2011-06-14 22:03:46 +00:00
parent 106f0ca2c0
commit 2851fcfcde
2 changed files with 67 additions and 9 deletions
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60
src/arch/arm.h
View File

@ -34,8 +34,66 @@ static int _arm_write(ArchPlugin * plugin, ArchInstruction * instruction,
{ {
ArchPluginHelper * helper = plugin->helper; ArchPluginHelper * helper = plugin->helper;
uint32_t opcode = instruction->opcode; uint32_t opcode = instruction->opcode;
ArchRegister * ar;
char const * p;
/* FIXME really implement */ switch(instruction->opcode & 0x0fffffff)
{
#if 1 /* FIXME implement */
case and:
case eor:
case sub:
case rsb:
case add:
case adc:
case sbc:
case rsc:
case tst:
case teq:
case cmp:
case cmn:
case orr:
case bic:
break;
#endif
case mov:
case mov | (0x1 << 20): /* movs */
case mvn:
case mvn | (0x1 << 20): /* mvns */
if(call->operands_cnt == 0) /* nop */
break;
/* first operand, Rd */
p = call->operands[0].value._register.name;
if((ar = helper->get_register_by_name_size(helper->arch,
p, 32)) == NULL)
return -1;
/* second operand, Rm */
opcode |= (ar->id << 12);
p = call->operands[1].value._register.name;
if((ar = helper->get_register_by_name_size(helper->arch,
p, 32)) == NULL)
return -1;
opcode |= ar->id;
break;
case mov | (0x1 << 25): /* mov (immediate) */
case mov | (0x1 << 25) | (0x1 << 20): /* movs (immediate) */
case mvn | (0x1 << 25): /* mvn (immediate) */
case mvn | (0x1 << 25) | (0x1 << 20): /* mvns (immediate) */
if(call->operands_cnt == 0) /* nop */
break;
/* first operand, Rd */
p = call->operands[0].value._register.name;
if((ar = helper->get_register_by_name_size(helper->arch,
p, 32)) == NULL)
return -1;
opcode |= (ar->id << 12);
/* FIXME immediate value */
break;
#if 1 /* FIXME really implement */
default:
break;
#endif
}
if(helper->write(helper->arch, &opcode, sizeof(opcode)) if(helper->write(helper->arch, &opcode, sizeof(opcode))
!= sizeof(opcode)) != sizeof(opcode))
return -1; return -1;

16
test/arm.S
View File

@ -70,14 +70,14 @@
ldreq %r0, %r0, %r0 ldreq %r0, %r0, %r0
mcr %r0, %r0, %r0 mcr %r0, %r0, %r0
mcreq %r0, %r0, %r0 mcreq %r0, %r0, %r0
mov %r5, %r4 mov %r4, %r0
moveq %r5, %r4 moveq %r5, %r1
mov %r5, $0x1 mov %r6, $0x1
moveq %r5, $0x2 moveq %r7, $0x2
movs %r5, %r4 movs %r8, %r4
moveqs %r5, %r4 moveqs %r9, %r5
movs %r5, $0x1 movs %r10, $0x1
moveqs %r5, $0x2 moveqs %r11, $0x2
mrc %r0, %r0, %r0 mrc %r0, %r0, %r0
mrceq %r0, %r0, %r0 mrceq %r0, %r0, %r0
mrs %r0, %cpsr mrs %r0, %cpsr