Added a few instructions
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6870bbd088
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@ -50,6 +50,7 @@
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/* operands */
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/* registers */
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#define OP_R8 AO_REGISTER(0, 8, 0)
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#define OP_R16 AO_REGISTER(0, 16, 0)
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#define OP_RW AO_REGISTER(0, W, 0)
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#define OP_al AO_REGISTER(AOF_IMPLICIT, REG_al_size, REG_al_id)
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#define OP_cl AO_REGISTER(AOF_IMPLICIT, REG_cl_size, REG_cl_id)
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@ -102,6 +103,7 @@
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/* mod r/m byte */
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#define AOF_I386_MODRM 0x2
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#define OP_R8_R AO_REGISTER(AOF_I386_MODRM, 8, 0)
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#define OP_R16_R AO_REGISTER(AOF_I386_MODRM, 16, 0)
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#define OP_RW_R AO_REGISTER(AOF_I386_MODRM, W, 0)
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#define OP_RM8_D0 AO_DREGISTER(AOF_I386_MODRM, 0, W, 0) /* 0x00 */
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#define OP_RM8_D8 AO_DREGISTER(AOF_I386_MODRM, 8, W, 0) /* 0x40 */
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@ -121,6 +123,7 @@
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#define OP_RMW_RW_R AO_REGISTER(AOF_I386_MODRM, W, 8) /* 0xc0 */
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/* constant values */
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#define OP_C1 AO_CONSTANT(AOF_IMPLICIT, 8, 0x01)
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#define OP_C3 AO_CONSTANT(AOF_IMPLICIT, 8, 0x03)
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/* immediate values */
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@ -228,6 +231,8 @@
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{ "addb", 0x83, OP1F, OP_RMW_D8+0,OP_S8, AOT_NONE },
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{ "addb", 0x83, OP1F, OP_RMW_DW+0,OP_S8, AOT_NONE },
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{ "add", 0x83, OP1F, OP_RMW_RW+0,OP_S8, AOT_NONE },
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/* ADDRSIZE 0x67 1 */
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{ "addrsize", 0x67, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
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/* AND 0x24 ib 1 al imm8 */
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{ "and", 0x24, OP1F, OP_al, OP_S8, AOT_NONE },
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/* AND 0x25 iW 1 AX immW */
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@ -788,6 +793,13 @@
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{ "jz", 0x0f84, OP2F, OP_SW, AOT_NONE, AOT_NONE },
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/* LAHF 0x9f 1 */
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{ "lahf", 0x9f, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
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#if 1 /* FIXME probably doesn't work at the moment */
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/* LEA 0x8d 1 rW m */
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{ "lea", 0x8d, OP1F, OP_RW_R, OP_RMW_D0, AOT_NONE },
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{ "lea", 0x8d, OP1F, OP_RW_R, OP_RMW_D8, AOT_NONE },
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{ "lea", 0x8d, OP1F, OP_RW_R, OP_RMW_DW, AOT_NONE },
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{ "lea", 0x8d, OP1F, OP_RW_R, OP_RMW_RW, AOT_NONE },
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#endif
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/* LEAVE 0xc9 1 */
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{ "leave", 0xc9, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
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/* LOCK 0xf0 1 */
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@ -831,6 +843,10 @@
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{ "mov", 0x8b, OP1F, OP_RW_R, OP_RMW_D8, AOT_NONE },
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{ "mov", 0x8b, OP1F, OP_RW_R, OP_RMW_DW, AOT_NONE },
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{ "mov", 0x8b, OP1F, OP_RW_R, OP_RMW_RW, AOT_NONE },
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#if 1 /* FIXME doesn't work properly */
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/* MOV 0x8e /r 1 Sreg r/m16 */
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#endif
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{ "mov", 0x8e, OP1F, OP_R16_R, OP_R16_R, AOT_NONE },
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/* MOV 0xa3 1 AX moffsW */
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{ "mov", 0xa3, OP1F, OP_AX, OP_SW, AOT_NONE },
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/* MOV 0xb0 +rb 1 r8 imm8 */
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@ -929,6 +945,8 @@
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{ "not", 0xf7, OP1F, OP_RMW_D8+2,AOT_NONE, AOT_NONE },
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{ "not", 0xf7, OP1F, OP_RMW_DW+2,AOT_NONE, AOT_NONE },
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{ "not", 0xf7, OP1F, OP_RMW_RW+2,AOT_NONE, AOT_NONE },
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/* OPSIZE 0x66 1 */
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{ "opsize", 0x66, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
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/* OR 0x0c ib 1 al imm8 */
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{ "or", 0x0c, OP1F, OP_al, OP_S8, AOT_NONE },
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/* OR 0x0d iW 1 AX immW */
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@ -1067,8 +1085,11 @@
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/* FIXME implement */
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/* ROR */
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/* FIXME implement */
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/* REP */
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/* FIXME implement */
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/* REP 0xf3a4 2 MOVS m8 */
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{ "rep movs", 0xf3a4, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
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/* REP 0xf3ab 2 STOS mW */
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{ "rep stos", 0xf3ab, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
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/* FIXME implement the rest */
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/* RET 0xc2 1 imm16 */
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{ "ret", 0xc2, OP1F, OP_U16, AOT_NONE, AOT_NONE },
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/* RET 0xca 1 imm16 */
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@ -1081,12 +1102,22 @@
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{ "rsm", 0x0faa, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
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/* SAHF 0x9e 1 */
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{ "sahf", 0x9e, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
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/* SAL 0xc0 /4 1 r/m8 imm8 */
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{ "sal", 0xc0, OP1F, OP_RM8_D0+4,OP_U8, AOT_NONE },
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{ "sal", 0xc0, OP1F, OP_RM8_D8+4,OP_U8, AOT_NONE },
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{ "sal", 0xc0, OP1F, OP_RM8_DW+4,OP_U8, AOT_NONE },
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{ "sal", 0xc0, OP1F, OP_RM8_R8+4,OP_U8, AOT_NONE },
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/* SAL 0xc1 /4 1 r/mW imm8 */
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{ "sal", 0xc1, OP1F, OP_RMW_D0+4,OP_U8, AOT_NONE },
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{ "sal", 0xc1, OP1F, OP_RMW_D8+4,OP_U8, AOT_NONE },
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{ "sal", 0xc1, OP1F, OP_RMW_DW+4,OP_U8, AOT_NONE },
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{ "sal", 0xc1, OP1F, OP_RMW_RW+4,OP_U8, AOT_NONE },
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/* FIXME implement */
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/* SAR 0xc0 /7 1 r/m8 imm8 */
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{ "sar", 0xc0, OP1F, OP_RM8_D0+7,OP_U8, AOT_NONE },
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{ "sar", 0xc0, OP1F, OP_RM8_D8+7,OP_U8, AOT_NONE },
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{ "sar", 0xc0, OP1F, OP_RM8_DW+7,OP_U8, AOT_NONE },
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{ "sar", 0xc0, OP1F, OP_RM8_R8+7,OP_U8, AOT_NONE },
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/* SAR 0xc1 /7 1 r/mW imm8 */
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{ "sar", 0xc1, OP1F, OP_RMW_D0+7,OP_U8, AOT_NONE },
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{ "sar", 0xc1, OP1F, OP_RMW_D8+7,OP_U8, AOT_NONE },
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@ -1177,6 +1208,11 @@
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{ "shld", 0x0fa5, OP2F, OP_RMW_D8, OP_RW_R, OP_cl },
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{ "shld", 0x0fa5, OP2F, OP_RMW_DW, OP_RW_R, OP_cl },
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{ "shld", 0x0fa5, OP2F, OP_RMW_RW, OP_RW_R, OP_cl },
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/* SHR 0xd0 /5 1 r/m8 1 */
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{ "shr", 0xd0, OP1F, OP_RM8_D0, OP_C1, AOT_NONE },
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{ "shr", 0xd0, OP1F, OP_RM8_D8, OP_C1, AOT_NONE },
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{ "shr", 0xd0, OP1F, OP_RM8_DW, OP_C1, AOT_NONE },
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{ "shr", 0xd0, OP1F, OP_RM8_R8, OP_C1, AOT_NONE },
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/* SHRD 0x0fac 2 r/mW rW imm8 */
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{ "shrd", 0x0fac, OP2F, OP_RMW_D0, OP_RW_R, OP_U8 },
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{ "shrd", 0x0fac, OP2F, OP_RMW_D8, OP_RW_R, OP_U8 },
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