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Improved the Dalvi diassembly and output some more

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This commit is contained in:
Pierre Pronchery 2011-04-23 23:20:09 +00:00
parent 442efe1151
commit 3a7bc16298
3 changed files with 92 additions and 95 deletions
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10
src/arch.c
View File

@ -444,13 +444,13 @@ static void _decode_print(off_t offset, ArchInstructionCall * call);
int arch_decode(Arch * arch)
{
ArchInstructionCall call;
off_t offset;
off_t offset = arch->buffer_pos;
if(arch->plugin->decode == NULL)
return -error_set_code(1, "%s: %s", arch->plugin->name,
"Disassembly not supported");
for(offset = arch->buffer_pos;
arch->plugin->decode(arch->plugin, &call) == 0;
printf("%08lx:\n", offset);
for(; arch->plugin->decode(arch->plugin, &call) == 0;
offset = arch->buffer_pos)
_decode_print(offset, &call);
return 0;
@ -458,12 +458,12 @@ int arch_decode(Arch * arch)
static void _decode_print(off_t offset, ArchInstructionCall * call)
{
char const * sep = "\t";
char const * sep = " ";
size_t i;
ArchOperand * ao;
char const * name;
printf("%08lx: %s", offset, call->name);
printf("%8lx: %-12s", offset, call->name);
for(i = 0; i < call->operands_cnt; i++)
{
ao = &call->operands[i];

14
src/arch/dalvik.c
View File

@ -143,6 +143,7 @@ static int _dalvik_decode(ArchPlugin * plugin, ArchInstructionCall * call)
DalvikDecode dd;
ArchPluginHelper * helper = plugin->helper;
uint8_t u8;
uint16_t u16;
ArchInstruction * ai;
size_t i;
@ -157,8 +158,16 @@ static int _dalvik_decode(ArchPlugin * plugin, ArchInstructionCall * call)
call->operands[2].type = AOT_NONE;
if((ai = helper->get_instruction_by_opcode(helper->arch, 8, u8))
== NULL)
/* FIXME check if it's a nop or return "dw" */
return -1;
{
u16 = u8 << 8;
if(helper->read(helper->arch, &u8, sizeof(u8)) != sizeof(u8))
return -1;
u16 = _htol16(u16 | u8);
if((ai = helper->get_instruction_by_opcode(helper->arch, 16,
u16)) == NULL)
/* FIXME return "dw" */
return -1;
}
call->name = ai->name;
call->operands[0].type = ai->op1;
call->operands[1].type = ai->op2;
@ -277,6 +286,7 @@ static int _decode_register(DalvikDecode * dd, size_t i)
}
else
return -1;
/* FIXME it could be a register above 256... */
if((ar = helper->get_register_by_id_size(helper->arch, id, 32)) == NULL)
return -1;
dd->call->operands[i].value._register.name = ar->name;

163
src/arch/dalvik.ins
View File

@ -28,6 +28,7 @@
#define OP_REGISTER AO_REGISTER(0, 32, 0)
#define OP_REG4 AO_REGISTER(AOF_DALVIK_REGSIZE, 32, 4)
#define OP_REG8 AO_REGISTER(AOF_DALVIK_REGSIZE, 32, 8)
#define OP_REG16 AO_REGISTER(AOF_DALVIK_REGSIZE, 32, 16)
/* immediate values */
#define OP_U4 AO_IMMEDIATE(0, 0, 4)
@ -37,15 +38,15 @@
#define OP_U64 AO_IMMEDIATE(0, 0, 64)
{ "add-double", 0xab, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
{ "add-double", 0xab, OP1F, OP_REG8, OP_REG8, OP_REG8 },
{ "add-double/2addr", 0xcb, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
{ "add-float", 0xa6, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
{ "add-float", 0xa6, OP1F, OP_REG8, OP_REG8, OP_REG8 },
{ "add-float/2addr", 0xc6, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
{ "add-int", 0x90, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
{ "add-int", 0x90, OP1F, OP_REG8, OP_REG8, OP_REG8 },
{ "add-int/2addr", 0xb0, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
{ "add-int/lit8", 0xd8, OP1F, OP_REG8, OP_REG8, OP_U8 },
{ "add-int/lit16", 0xd0, OP1F, OP_REGISTER, OP_U16, AOT_NONE },
{ "add-long", 0x9b, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
{ "add-long", 0x9b, OP1F, OP_REG8, OP_REG8, OP_REG8 },
{ "add-long/2addr", 0xbb, OP1F, OP_REG4, OP_REG4, AOT_NONE },
{ "aget", 0x44, OP1F, OP_REG8, OP_REG8, OP_REG8 },
{ "aget-boolean", 0x47, OP1F, OP_REG8, OP_REG8, OP_REG8 },
@ -54,15 +55,15 @@
{ "aget-object", 0x46, OP1F, OP_REG8, OP_REG8, OP_REG8 },
{ "aget-short", 0x4a, OP1F, OP_REG8, OP_REG8, OP_REG8 },
{ "aget-wide", 0x45, OP1F, OP_REG8, OP_REG8, OP_REG8 },
{ "and-int", 0x95, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
{ "and-int", 0x95, OP1F, OP_REG8, OP_REG8, OP_REG8 },
#if 1 /* XXX implement correctly */
{ "and-int/2addr", 0xb5, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
{ "and-int/2addr", 0xb5, OP1F, OP_REG4, OP_REG4, AOT_NONE },
#endif
{ "and-int/lit8", 0xdd, OP1F, OP_REGISTER, OP_REGISTER, OP_U8 },
{ "and-int/lit16", 0xd5, OP1F, OP_REGISTER, OP_U16, AOT_NONE },
{ "and-long", 0xa0, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
{ "and-long", 0xa0, OP1F, OP_REG8, OP_REG8, OP_REG8 },
#if 1 /* XXX implement correctly */
{ "and-long/2addr", 0xc0, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
{ "and-long/2addr", 0xc0, OP1F, OP_REG4, OP_REG4, AOT_NONE },
#endif
{ "aput", 0x4b, OP1F, OP_REG8, OP_REG8, OP_REG8 },
{ "aput-boolean", 0x4e, OP1F, OP_REG8, OP_REG8, OP_REG8 },
@ -72,7 +73,7 @@
{ "aput-short", 0x51, OP1F, OP_REG8, OP_REG8, OP_REG8 },
{ "aput-wide", 0x4c, OP1F, OP_REG8, OP_REG8, OP_REG8 },
#if 1 /* XXX implement correctly */
{ "array-length", 0x21, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
{ "array-length", 0x21, OP1F, OP_REG4, OP_REG4, AOT_NONE },
{ "check-cast", 0x1f, OP1F, OP_REGISTER, OP_U16, AOT_NONE },
#endif
{ "cmp-long", 0x31, OP1F, OP_REG8, OP_REG8, OP_REG8 },
@ -80,55 +81,51 @@
{ "cmpg-float", 0x2e, OP1F, OP_REG8, OP_REG8, OP_REG8 },
{ "cmpl-double", 0x2f, OP1F, OP_REG8, OP_REG8, OP_REG8 },
{ "cmpl-float", 0x2d, OP1F, OP_REG8, OP_REG8, OP_REG8 },
{ "const", 0x14, OP1F, OP_REGISTER, OP_U32, AOT_NONE },
{ "const", 0x14, OP1F, OP_REG8, OP_U32, AOT_NONE },
{ "const/4", 0x12, OP1F, OP_REG4, OP_U4, AOT_NONE },
{ "const/16", 0x13, OP1F, OP_REGISTER, OP_U16, AOT_NONE },
{ "const/high16", 0x15, OP1F, OP_REGISTER, OP_U16, AOT_NONE },
{ "const-class", 0x1c, OP1F, OP_REGISTER, OP_U16, AOT_NONE },
{ "const/16", 0x13, OP1F, OP_REG8, OP_U16, AOT_NONE },
{ "const/high16", 0x15, OP1F, OP_REG8, OP_U16, AOT_NONE },
{ "const-class", 0x1c, OP1F, OP_REG8, OP_U16, AOT_NONE },
{ "const-string", 0x1a, OP1F, OP_REG8, OP_U16, AOT_NONE },
{ "const-wide", 0x18, OP1F, OP_REGISTER, OP_U64, AOT_NONE },
{ "const-wide", 0x18, OP1F, OP_REG8, OP_U64, AOT_NONE },
{ "const-wide/16", 0x16, OP1F, OP_REG8, OP_U16, AOT_NONE },
{ "const-wide/32", 0x17, OP1F, OP_REGISTER, OP_U32, AOT_NONE },
{ "div-double", 0xae, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
{ "const-wide/32", 0x17, OP1F, OP_REG8, OP_U32, AOT_NONE },
{ "div-double", 0xae, OP1F, OP_REG8, OP_REG8, OP_REG8 },
{ "div-double/2addr", 0xce, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
{ "div-float", 0xa9, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
{ "div-float", 0xa9, OP1F, OP_REG8, OP_REG8, OP_REG8 },
{ "div-float/2addr", 0xc9, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
{ "div-int", 0x93, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
{ "div-int", 0x93, OP1F, OP_REG8, OP_REG8, OP_REG8 },
#if 1 /* XXX implement correctly */
{ "div-int/2addr", 0xb3, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
#endif
{ "div-int/lit8", 0xdb, OP1F, OP_REGISTER, OP_REGISTER, OP_U8 },
{ "div-int/lit16", 0xd3, OP1F, OP_REGISTER, OP_U16, AOT_NONE },
{ "div-long", 0x9e, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
#if 1 /* XXX implement correctly */
{ "div-long", 0x9e, OP1F, OP_REG8, OP_REG8, OP_REG8 },
{ "div-long/2addr", 0xbe, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
{ "double-to-float", 0x8c, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
{ "double-to-int", 0x8a, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
{ "double-to-long", 0x8b, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
#if 1 /* XXX really implement */
{ "fill-array-data", 0x26, OP1F, OP_REGISTER, OP_U32, AOT_NONE },
{ "filled-new-array", 0x24, OP1F, OP_REGISTER, OP_U32, AOT_NONE },
{ "fill-array-data", 0x26, OP1F, OP_REG8, OP_U32, AOT_NONE },
{ "filled-new-array", 0x24, OP1F, OP_REG8, OP_U32, AOT_NONE },
{ "filled-new-array-range",
0x25, OP1F, OP_REGISTER, OP_U32, AOT_NONE },
#endif
{ "float-to-double", 0x89, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
{ "float-to-int", 0x8a, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
{ "float-to-long", 0x88, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
#endif
0x25, OP1F, OP_REG8, OP_U32, AOT_NONE },
{ "float-to-double", 0x89, OP1F, OP_REG4, OP_REG4, AOT_NONE },
{ "float-to-int", 0x8a, OP1F, OP_REG4, OP_REG4, AOT_NONE },
{ "float-to-long", 0x88, OP1F, OP_REG4, OP_REG4, AOT_NONE },
{ "goto", 0x28, OP1F, OP_U8, AOT_NONE, AOT_NONE },
{ "goto/16", 0x2900, OP2F, OP_U16, AOT_NONE, AOT_NONE },
{ "if-eq", 0x32, OP1F, OP_v0, OP_REGISTER, OP_U16 },
{ "if-eq", 0x32, OP1F, OP_REG4, OP_REG4, OP_U16 },
{ "if-eqz", 0x38, OP1F, OP_REG8, OP_U16, AOT_NONE },
{ "if-ge", 0x35, OP1F, OP_v0, OP_REGISTER, OP_U16 },
{ "if-ge", 0x35, OP1F, OP_REG4, OP_REG4, OP_U16 },
{ "if-gez", 0x3b, OP1F, OP_REG8, OP_U16, AOT_NONE },
{ "if-gt", 0x36, OP1F, OP_v0, OP_REGISTER, OP_U16 },
{ "if-gt", 0x36, OP1F, OP_REG4, OP_REG4, OP_U16 },
{ "if-gtz", 0x3c, OP1F, OP_REG8, OP_U16, AOT_NONE },
{ "if-le", 0x37, OP1F, OP_v0, OP_REGISTER, OP_U16 },
{ "if-le", 0x37, OP1F, OP_REG4, OP_REG4, OP_U16 },
{ "if-lez", 0x3d, OP1F, OP_REG8, OP_U16, AOT_NONE },
{ "if-lt", 0x34, OP1F, OP_v0, OP_REGISTER, OP_U16 },
{ "if-lt", 0x34, OP1F, OP_REG4, OP_REG4, OP_U16 },
{ "if-ltz", 0x3a, OP1F, OP_REG8, OP_U16, AOT_NONE },
{ "if-ne", 0x33, OP1F, OP_v0, OP_REGISTER, OP_U16 },
{ "if-nez", 0x39, OP1F, OP_REGISTER, OP_U16, AOT_NONE },
{ "if-ne", 0x33, OP1F, OP_REG4, OP_REG4, OP_U16 },
{ "if-nez", 0x39, OP1F, OP_REG8, OP_U16, AOT_NONE },
{ "iget", 0x52, OP1F, OP_REG4, OP_REG4, OP_U16 },
{ "iget-boolean", 0x55, OP1F, OP_REG4, OP_REG4, OP_U16 },
{ "iget-byte", 0x56, OP1F, OP_REG4, OP_REG4, OP_U16 },
@ -141,11 +138,11 @@
{ "int-to-float", 0x82, OP1F, OP_REG4, OP_REG4, AOT_NONE },
{ "int-to-long", 0x81, OP1F, OP_REG4, OP_REG4, AOT_NONE },
{ "int-to-short", 0x8f, OP1F, OP_REG4, OP_REG4, AOT_NONE },
{ "invoke-direct", 0x70, OP1F, OP_U8, OP_U16, OP_U16 },
{ "invoke-direct/range",0x76, OP1F, OP_U8, OP_U16, OP_U16 },
{ "invoke-interface", 0x72, OP1F, OP_U8, OP_U16, OP_U16 },
{ "invoke-direct", 0x70, OP1F, OP_U8, OP_U16, OP_U16 },
{ "invoke-direct/range",0x76, OP1F, OP_U8, OP_U16, OP_U16 },
{ "invoke-interface", 0x72, OP1F, OP_U8, OP_U16, OP_U16 },
{ "invoke-interface-range",
0x78, OP1F, OP_U8, OP_U16, OP_U16 },
0x78, OP1F, OP_U8, OP_U16, OP_U16 },
{ "invoke-static", 0x71, OP1F, OP_U8, OP_U16, OP_U16 },
{ "invoke-static/range",0x77, OP1F, OP_U8, OP_U16, OP_U16 },
{ "invoke-super", 0x6f, OP1F, OP_U8, OP_U16, OP_U16 },
@ -163,36 +160,34 @@
{ "long-to-double", 0x86, OP1F, OP_REG4, OP_REG4, AOT_NONE },
{ "long-to-float", 0x85, OP1F, OP_REG4, OP_REG4, AOT_NONE },
{ "long-to-int", 0x84, OP1F, OP_REG4, OP_REG4, AOT_NONE },
{ "monitor-enter", 0x1d, OP1F, OP_REGISTER, AOT_NONE, AOT_NONE },
{ "monitor-exit", 0x1e, OP1F, OP_REGISTER, AOT_NONE, AOT_NONE },
{ "monitor-enter", 0x1d, OP1F, OP_REG8, AOT_NONE, AOT_NONE },
{ "monitor-exit", 0x1e, OP1F, OP_REG8, AOT_NONE, AOT_NONE },
{ "move", 0x01, OP1F, OP_REG4, OP_REG4, AOT_NONE },
{ "move/16", 0x03, OP1F, OP_REGISTER, OP_REGISTER, AOT_NONE },
{ "move/from16", 0x02, OP1F, OP_REGISTER, OP_REGISTER, AOT_NONE },
{ "move-exception", 0x0d, OP1F, OP_REGISTER, AOT_NONE, AOT_NONE },
#if 1 /* XXX really implement */
{ "move-object", 0x07, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
{ "move-object/16", 0x09, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
{ "move-object/from16", 0x08, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
#endif
{ "move/16", 0x03, OP1F, OP_REG16, OP_REG8, AOT_NONE },
{ "move/from16", 0x02, OP1F, OP_REG8, OP_REG16, AOT_NONE },
{ "move-exception", 0x0d, OP1F, OP_REG8, AOT_NONE, AOT_NONE },
{ "move-object", 0x07, OP1F, OP_REG4, OP_REG4, AOT_NONE },
{ "move-object/16", 0x09, OP1F, OP_REG4, OP_REG4, AOT_NONE },
{ "move-object/from16", 0x08, OP1F, OP_REG4, OP_REG4, AOT_NONE },
{ "move-result", 0x0a, OP1F, OP_REG8, AOT_NONE, AOT_NONE },
{ "move-result-object", 0x0c, OP1F, OP_REG8, AOT_NONE, AOT_NONE },
{ "move-result-wide", 0x0b, OP1F, OP_REG8, AOT_NONE, AOT_NONE },
#if 1 /* XXX really implement */
{ "move-wide", 0x04, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
{ "move-wide", 0x04, OP1F, OP_REG4, OP_REG4, AOT_NONE },
#endif
{ "move-wide/16", 0x06, OP1F, OP_REGISTER, OP_REGISTER, AOT_NONE },
{ "move-wide/from16", 0x05, OP1F, OP_REGISTER, OP_REGISTER, AOT_NONE },
{ "mul-double", 0xad, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
{ "mul-double", 0xad, OP1F, OP_REG8, OP_REG8, OP_REG8 },
{ "mul-double/2addr", 0xcd, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
{ "mul-float", 0xa8, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
{ "mul-float", 0xa8, OP1F, OP_REG8, OP_REG8, OP_REG8 },
{ "mul-float/2addr", 0xc8, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
{ "mul-int", 0x92, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
{ "mul-int", 0x92, OP1F, OP_REG8, OP_REG8, OP_REG8 },
#if 1 /* XXX implement correctly */
{ "mul-int/2addr", 0xb2, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
#endif
{ "mul-int/lit8", 0xda, OP1F, OP_REGISTER, OP_REGISTER, OP_U8 },
{ "mul-int/lit16", 0xd2, OP1F, OP_REGISTER, OP_U16, AOT_NONE },
{ "mul-long", 0x9d, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
{ "mul-long", 0x9d, OP1F, OP_REG8, OP_REG8, OP_REG8 },
#if 1 /* XXX implement correctly */
{ "mul-long/2addr", 0xbd, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
{ "neg-double", 0x80, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
@ -208,35 +203,35 @@
{ "not-int", 0x7c, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
{ "not-long", 0x7e, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
#endif
{ "or-int", 0x96, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
{ "or-int", 0x96, OP1F, OP_REG8, OP_REG8, OP_REG8 },
#if 1 /* XXX implement correctly */
{ "or-int/2addr", 0xb6, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
#endif
{ "or-int/lit8", 0xdb, OP1F, OP_REGISTER, OP_REGISTER, OP_U8 },
{ "or-int/lit16", 0xd6, OP1F, OP_REGISTER, OP_U16, AOT_NONE },
{ "or-long", 0xa1, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
{ "or-long", 0xa1, OP1F, OP_REG8, OP_REG8, OP_REG8 },
#if 1 /* XXX implement correctly */
{ "or-long/2addr", 0xc1, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
#endif
{ "rem-double", 0xaf, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
{ "rem-double", 0xaf, OP1F, OP_REG8, OP_REG8, OP_REG8 },
{ "rem-double/2addr", 0xcf, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
{ "rem-float", 0xaa, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
{ "rem-float", 0xaa, OP1F, OP_REG8, OP_REG8, OP_REG8 },
{ "rem-float/2addr", 0xca, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
{ "rem-int", 0x94, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
{ "rem-int", 0x94, OP1F, OP_REG8, OP_REG8, OP_REG8 },
#if 1 /* XXX implement correctly */
{ "rem-int/2addr", 0xb4, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
#endif
{ "rem-int/lit8", 0xdc, OP1F, OP_REGISTER, OP_REGISTER, OP_U8 },
{ "rem-int/lit16", 0xd4, OP1F, OP_REGISTER, OP_U16, AOT_NONE },
{ "rem-long", 0x9f, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
{ "rem-long", 0x9f, OP1F, OP_REG8, OP_REG8, OP_REG8 },
#if 1 /* XXX implement correctly */
{ "rem-long/2addr", 0xbf, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
#endif
{ "return", 0x0f, OP1F, OP_REGISTER, AOT_NONE, AOT_NONE },
{ "return-object", 0x11, OP1F, OP_REGISTER, AOT_NONE, AOT_NONE },
{ "return", 0x0f, OP1F, OP_REG8, AOT_NONE, AOT_NONE },
{ "return-object", 0x11, OP1F, OP_REG8, AOT_NONE, AOT_NONE },
{ "return-void", 0x0e00, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
{ "return-void", 0x0e, OP1F, OP_U8, AOT_NONE, AOT_NONE },
{ "return-wide", 0x10, OP1F, OP_REGISTER, AOT_NONE, AOT_NONE },
{ "return-wide", 0x10, OP1F, OP_REG8, AOT_NONE, AOT_NONE },
{ "sget", 0x60, OP1F, OP_REG8, OP_U16, AOT_NONE },
{ "sget-boolean", 0x63, OP1F, OP_REG8, OP_U16, AOT_NONE },
{ "sget-byte", 0x64, OP1F, OP_REG8, OP_U16, AOT_NONE },
@ -244,21 +239,21 @@
{ "sget-object", 0x62, OP1F, OP_REG8, OP_U16, AOT_NONE },
{ "sget-short", 0x66, OP1F, OP_REG8, OP_U16, AOT_NONE },
{ "sget-wide", 0x61, OP1F, OP_REG8, OP_U16, AOT_NONE },
{ "shl-int", 0x98, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
{ "shl-int", 0x98, OP1F, OP_REG8, OP_REG8, OP_REG8 },
#if 1 /* XXX implement correctly */
{ "shl-int/2addr", 0xb8, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
#endif
{ "shl-int/lit8", 0xe0, OP1F, OP_REGISTER, OP_REGISTER, OP_U8 },
{ "shl-long", 0xa3, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
{ "shl-long", 0xa3, OP1F, OP_REG8, OP_REG8, OP_REG8 },
#if 1 /* XXX implement correctly */
{ "shl-long/2addr", 0xc3, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
#endif
{ "shr-int", 0x99, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
{ "shr-int", 0x99, OP1F, OP_REG8, OP_REG8, OP_REG8 },
#if 1 /* XXX implement correctly */
{ "shr-int/2addr", 0xb9, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
#endif
{ "shr-int/lit8", 0xe1, OP1F, OP_REGISTER, OP_REGISTER, OP_U8 },
{ "shr-long", 0xa4, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
{ "shr-long", 0xa4, OP1F, OP_REG8, OP_REG8, OP_REG8 },
#if 1 /* XXX implement correctly */
{ "shr-long/2addr", 0xc4, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
{ "sparse-switch", 0x2c, OP1F, OP_REGISTER, OP_U32, AOT_NONE },
@ -270,37 +265,29 @@
{ "sput-object", 0x69, OP1F, OP_REG8, OP_U16, AOT_NONE },
{ "sput-short", 0x6d, OP1F, OP_REG8, OP_U16, AOT_NONE },
{ "sput-wide", 0x68, OP1F, OP_REG8, OP_U16, AOT_NONE },
{ "sub-double", 0xac, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
{ "sub-double", 0xac, OP1F, OP_REG8, OP_REG8, OP_REG8 },
{ "sub-double/2addr", 0xcc, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
{ "sub-float", 0xa7, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
{ "sub-float", 0xa7, OP1F, OP_REG8, OP_REG8, OP_REG8 },
{ "sub-float/2addr", 0xc7, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
{ "sub-int", 0x91, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
{ "sub-int", 0x91, OP1F, OP_REG8, OP_REG8, OP_REG8 },
#if 1 /* XXX implement correctly */
{ "sub-int/2addr", 0xb1, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
#endif
{ "sub-int/lit8", 0xd9, OP1F, OP_REGISTER, OP_REGISTER, OP_U8 },
{ "sub-int/lit16", 0xd1, OP1F, OP_REGISTER, OP_U16, AOT_NONE },
{ "sub-long", 0x9c, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
#if 1 /* XXX implement correctly */
{ "sub-long/2addr", 0xbc, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
#endif
{ "sub-long", 0x9c, OP1F, OP_REG8, OP_REG8, OP_REG8 },
{ "sub-long/2addr", 0xbc, OP1F, OP_REG4, OP_REG4, AOT_NONE },
{ "throw", 0x27, OP1F, OP_REGISTER, AOT_NONE, AOT_NONE },
{ "ushr-int", 0x9a, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
#if 1 /* XXX implement correctly */
{ "ushr-int/2addr", 0xba, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
#endif
{ "ushr-int", 0x9a, OP1F, OP_REG8, OP_REG8, OP_REG8 },
{ "ushr-int/2addr", 0xba, OP1F, OP_REG4, OP_REG4, AOT_NONE },
{ "ushr-int/lit8", 0xe2, OP1F, OP_REGISTER, OP_REGISTER, OP_U8 },
{ "ushr-long", 0xa5, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
#if 1 /* XXX implement correctly */
{ "ushr-long/2addr", 0xc5, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
#endif
{ "xor-int", 0x97, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
{ "ushr-long", 0xa5, OP1F, OP_REG8, OP_REG8, OP_REG8 },
{ "ushr-long/2addr", 0xc5, OP1F, OP_REG4, OP_REG4, AOT_NONE },
{ "xor-int", 0x97, OP1F, OP_REG8, OP_REG8, OP_REG8 },
#if 1 /* XXX implement correctly */
{ "xor-int/2addr", 0xb7, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
#endif
{ "xor-int/lit8", 0xdf, OP1F, OP_REGISTER, OP_REGISTER, OP_U8 },
{ "xor-int/lit16", 0xd7, OP1F, OP_REGISTER, OP_U16, AOT_NONE },
{ "xor-long", 0xa2, OP1F, OP_REGISTER, OP_REGISTER, OP_REGISTER },
#if 1 /* XXX implement correctly */
{ "xor-long/2addr", 0xc2, OP_v0, OP_REGISTER, AOT_NONE, AOT_NONE },
#endif
{ "xor-long", 0xa2, OP1F, OP_REG8, OP_REG8, OP_REG8 },
{ "xor-long/2addr", 0xc2, OP1F, OP_REG4, OP_REG4, AOT_NONE },