Deassembling some instructions for the Yasep processor as well
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389f82aef4
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@ -43,6 +43,7 @@ static ArchInstruction _yasep_instructions[] =
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/* plug-in */
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static int _yasep_encode(ArchPlugin * plugin, ArchInstruction * instruction,
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ArchInstructionCall * call);
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static int _yasep_decode(ArchPlugin * plugin, ArchInstructionCall * call);
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/* protected */
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@ -57,7 +58,7 @@ ArchPlugin arch_plugin =
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NULL,
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NULL,
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_yasep_encode,
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NULL
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_yasep_decode
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};
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@ -103,3 +104,23 @@ static int _encode_32(ArchPlugin * plugin, ArchInstruction * instruction,
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return -1;
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return 0;
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}
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/* yasep_decode */
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static int _yasep_decode(ArchPlugin * plugin, ArchInstructionCall * call)
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{
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ArchPluginHelper * helper = plugin->helper;
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uint16_t u16;
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uint16_t opcode;
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ArchInstruction * ai;
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if(helper->read(helper->arch, &u16, sizeof(u16)) != sizeof(u16))
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return -1;
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u16 = _htob16(u16);
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opcode = u16 & 0x00ff;
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if((ai = helper->get_instruction_by_opcode(helper->arch, 16, opcode))
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== NULL)
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return -1;
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call->name = ai->name;
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return 0;
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}
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@ -34,7 +34,60 @@
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#define OP_SND AO_REGISTER(0, 32, 0)
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/* instructions */
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{ "add", OPIR(0x0c), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "add", OPRR(0x0c), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "add", OPIRL(0x0c),OPIRLF, AO_2(OP_SI4, OP_IMM16) },
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{ "add", OPRRL(0x0c),OPRRLF, AO_3(OP_SND, OP_SI4, OP_DST3) },
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{ "add", OPIR(0x03), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "add", OPRR(0x03), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "add", OPIRL(0x03),OPIRLF, AO_2(OP_SI4, OP_IMM16) },
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{ "add", OPRRL(0x03),OPRRLF, AO_3(OP_SND, OP_SI4, OP_DST3) },
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{ "and", OPIR(0x02), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "and", OPRR(0x02), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "and", OPIRL(0x02),OPIRLF, AO_2(OP_SI4, OP_IMM16) },
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{ "and", OPRRL(0x02),OPRRLF, AO_3(OP_SND, OP_SI4, OP_DST3) },
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{ "andn", OPRR(0x0a), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "cmps", OPRR(0x1b), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "cmpu", OPRR(0x13), OPRRF, AO_2(OP_SI4, OP_SND) },
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#if 0 /* XXX aliases */
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{ "esb", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "esh", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "ezb", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "ezh", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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#endif
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{ "get", OPRR(0x05), OPRRF, AO_2(OP_SI4, OP_SND) },
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#if 0 /* XXX aliases */
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{ "ib", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "ih", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "ihh", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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#endif
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{ "lsb", OPRR(0x18), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "lsh", OPRR(0x38), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "lzb", OPRR(0x10), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "lzh", OPRR(0x30), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "mov", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "mul8h", OPRR(0x0c), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "mul8l", OPRR(0x04), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "muli", OPRR(0x14), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "nand", OPRR(0x12), OPRRF, AO_2(OP_SI4, OP_SND) },
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#if 0 /* XXX alias */
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{ "neg", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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#endif
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{ "nor", OPRR(0x2a), OPRRF, AO_2(OP_SI4, OP_SND) },
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#if 0 /* XXX alias */
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{ "not", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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#endif
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{ "or", OPRR(0x1a), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "orn", OPRR(0x22), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "put", OPRR(0x0d), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "rol", OPRR(0x21), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "ror", OPRR(0x19), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "sar", OPRR(0x09), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "sb", OPRR(0x08), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "sh", OPRR(0x20), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "shh", OPRR(0x28), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "shl", OPRR(0x11), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "shr", OPRR(0x01), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "smax", OPRR(0x3b), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "smin", OPRR(0x33), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "sub", OPRR(0x0b), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "umax", OPRR(0x2b), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "umin", OPRR(0x23), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "xor", OPRR(0x32), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "xorn", OPRR(0x3a), OPRRF, AO_2(OP_SI4, OP_SND) },
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33
test/yasep.S
33
test/yasep.S
@ -1,3 +1,36 @@
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/* $Id$ */
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.text
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add %r0, %r1
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and %r0, %r1
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andn %r0, %r1
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cmps %r0, %r1
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cmpu %r0, %r1
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get %r0, %r1
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lsb %r0, %r1
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lsh %r0, %r1
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lzb %r0, %r1
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lzh %r0, %r1
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mov %r0, %r1
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mul8h %r0, %r1
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mul8l %r0, %r1
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muli %r0, %r1
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nand %r0, %r1
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nor %r0, %r1
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or %r0, %r1
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orn %r0, %r1
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put %r0, %r1
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rol %r0, %r1
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ror %r0, %r1
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sar %r0, %r1
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sb %r0, %r1
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sh %r0, %r1
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shh %r0, %r1
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shl %r0, %r1
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shr %r0, %r1
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smax %r0, %r1
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smin %r0, %r1
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sub %r0, %r1
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umax %r0, %r1
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umin %r0, %r1
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xor %r0, %r1
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xorn %r0, %r1
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