Deassembling some instructions for the Yasep processor as well

This commit is contained in:
Pierre Pronchery 2011-11-28 01:04:29 +00:00
parent 389f82aef4
commit 560b0e9f07
3 changed files with 112 additions and 5 deletions

View File

@ -43,6 +43,7 @@ static ArchInstruction _yasep_instructions[] =
/* plug-in */
static int _yasep_encode(ArchPlugin * plugin, ArchInstruction * instruction,
ArchInstructionCall * call);
static int _yasep_decode(ArchPlugin * plugin, ArchInstructionCall * call);
/* protected */
@ -57,7 +58,7 @@ ArchPlugin arch_plugin =
NULL,
NULL,
_yasep_encode,
NULL
_yasep_decode
};
@ -103,3 +104,23 @@ static int _encode_32(ArchPlugin * plugin, ArchInstruction * instruction,
return -1;
return 0;
}
/* yasep_decode */
static int _yasep_decode(ArchPlugin * plugin, ArchInstructionCall * call)
{
ArchPluginHelper * helper = plugin->helper;
uint16_t u16;
uint16_t opcode;
ArchInstruction * ai;
if(helper->read(helper->arch, &u16, sizeof(u16)) != sizeof(u16))
return -1;
u16 = _htob16(u16);
opcode = u16 & 0x00ff;
if((ai = helper->get_instruction_by_opcode(helper->arch, 16, opcode))
== NULL)
return -1;
call->name = ai->name;
return 0;
}

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@ -34,7 +34,60 @@
#define OP_SND AO_REGISTER(0, 32, 0)
/* instructions */
{ "add", OPIR(0x0c), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "add", OPRR(0x0c), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "add", OPIRL(0x0c),OPIRLF, AO_2(OP_SI4, OP_IMM16) },
{ "add", OPRRL(0x0c),OPRRLF, AO_3(OP_SND, OP_SI4, OP_DST3) },
{ "add", OPIR(0x03), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "add", OPRR(0x03), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "add", OPIRL(0x03),OPIRLF, AO_2(OP_SI4, OP_IMM16) },
{ "add", OPRRL(0x03),OPRRLF, AO_3(OP_SND, OP_SI4, OP_DST3) },
{ "and", OPIR(0x02), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "and", OPRR(0x02), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "and", OPIRL(0x02),OPIRLF, AO_2(OP_SI4, OP_IMM16) },
{ "and", OPRRL(0x02),OPRRLF, AO_3(OP_SND, OP_SI4, OP_DST3) },
{ "andn", OPRR(0x0a), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "cmps", OPRR(0x1b), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "cmpu", OPRR(0x13), OPRRF, AO_2(OP_SI4, OP_SND) },
#if 0 /* XXX aliases */
{ "esb", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "esh", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "ezb", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "ezh", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
#endif
{ "get", OPRR(0x05), OPRRF, AO_2(OP_SI4, OP_SND) },
#if 0 /* XXX aliases */
{ "ib", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "ih", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "ihh", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
#endif
{ "lsb", OPRR(0x18), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "lsh", OPRR(0x38), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "lzb", OPRR(0x10), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "lzh", OPRR(0x30), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "mov", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "mul8h", OPRR(0x0c), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "mul8l", OPRR(0x04), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "muli", OPRR(0x14), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "nand", OPRR(0x12), OPRRF, AO_2(OP_SI4, OP_SND) },
#if 0 /* XXX alias */
{ "neg", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
#endif
{ "nor", OPRR(0x2a), OPRRF, AO_2(OP_SI4, OP_SND) },
#if 0 /* XXX alias */
{ "not", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
#endif
{ "or", OPRR(0x1a), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "orn", OPRR(0x22), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "put", OPRR(0x0d), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "rol", OPRR(0x21), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "ror", OPRR(0x19), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "sar", OPRR(0x09), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "sb", OPRR(0x08), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "sh", OPRR(0x20), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "shh", OPRR(0x28), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "shl", OPRR(0x11), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "shr", OPRR(0x01), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "smax", OPRR(0x3b), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "smin", OPRR(0x33), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "sub", OPRR(0x0b), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "umax", OPRR(0x2b), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "umin", OPRR(0x23), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "xor", OPRR(0x32), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "xorn", OPRR(0x3a), OPRRF, AO_2(OP_SI4, OP_SND) },

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@ -1,3 +1,36 @@
/* $Id$ */
.text
add %r0, %r1
and %r0, %r1
andn %r0, %r1
cmps %r0, %r1
cmpu %r0, %r1
get %r0, %r1
lsb %r0, %r1
lsh %r0, %r1
lzb %r0, %r1
lzh %r0, %r1
mov %r0, %r1
mul8h %r0, %r1
mul8l %r0, %r1
muli %r0, %r1
nand %r0, %r1
nor %r0, %r1
or %r0, %r1
orn %r0, %r1
put %r0, %r1
rol %r0, %r1
ror %r0, %r1
sar %r0, %r1
sb %r0, %r1
sh %r0, %r1
shh %r0, %r1
shl %r0, %r1
shr %r0, %r1
smax %r0, %r1
smin %r0, %r1
sub %r0, %r1
umax %r0, %r1
umin %r0, %r1
xor %r0, %r1
xorn %r0, %r1