From 60b8d522481774a3c8dcb97284a46d903c20721a Mon Sep 17 00:00:00 2001 From: Pierre Pronchery Date: Sun, 17 Apr 2011 05:53:20 +0000 Subject: [PATCH] Added some more instructions for "add" --- src/arch/i386.ins | 49 +++++++++++++++++++++++++++++++++++++---------- 1 file changed, 39 insertions(+), 10 deletions(-) diff --git a/src/arch/i386.ins b/src/arch/i386.ins index 137b3ee..144f58f 100644 --- a/src/arch/i386.ins +++ b/src/arch/i386.ins @@ -96,19 +96,48 @@ { "adc", 0x83, OP1F, OP_RMW_D8+2,OP_S8, AOT_NONE }, { "adc", 0x83, OP1F, OP_RMW_DW+2,OP_S8, AOT_NONE }, { "adc", 0x83, OP1F, OP_RMW_RW+2,OP_S8, AOT_NONE }, +/* ADD 0x00 /r 1 r/m8 r8 */ +{ "add", 0x00, OP1F, OP_RM8_D0_R,OP_R8, AOT_NONE }, +{ "add", 0x00, OP1F, OP_RM8_D8_R,OP_R8, AOT_NONE }, +{ "add", 0x00, OP1F, OP_RM8_DW_R,OP_R8, AOT_NONE }, +{ "add", 0x00, OP1F, OP_RM8_R8_R,OP_R8, AOT_NONE }, +/* ADD 0x01 /r 1 r/mW rW */ +{ "add", 0x01, OP1F, OP_RMW_D0_R,OP_RW, AOT_NONE }, +{ "add", 0x01, OP1F, OP_RMW_D8_R,OP_RW, AOT_NONE }, +{ "add", 0x01, OP1F, OP_RMW_DW_R,OP_RW, AOT_NONE }, +{ "add", 0x01, OP1F, OP_RMW_RW_R,OP_RW, AOT_NONE }, +/* ADD 0x02 /r 1 r8 r/m8 */ +#if 1 /* FIXME probably doesn't work at the moment */ +{ "add", 0x02, OP1F, OP_RM8_R8_R,OP_RM8_D0_R,AOT_NONE }, +{ "add", 0x02, OP1F, OP_RM8_R8_R,OP_RM8_D8_R,AOT_NONE }, +{ "add", 0x02, OP1F, OP_RM8_R8_R,OP_RM8_DW_R,AOT_NONE }, +{ "add", 0x02, OP1F, OP_RM8_R8_R,OP_RM8_R8_R,AOT_NONE }, +#endif +/* ADD 0x03 /r 1 rW r/mW */ +#if 1 /* FIXME probably doesn't work at the moment */ +{ "add", 0x03, OP1F, OP_RMW_RW_R,OP_RMW_D0_R,AOT_NONE }, +{ "add", 0x03, OP1F, OP_RMW_RW_R,OP_RMW_D8_R,AOT_NONE }, +{ "add", 0x03, OP1F, OP_RMW_RW_R,OP_RMW_DW_R,AOT_NONE }, +{ "add", 0x03, OP1F, OP_RMW_RW_R,OP_RMW_RW_R,AOT_NONE }, +#endif /* ADD 0x04 ib 1 al imm8 */ -{ "add", 0x04, OP1F, OP_al, OP_U8, AOT_NONE }, +{ "add", 0x04, OP1F, OP_al, OP_S8, AOT_NONE }, /* ADD 0x05 iW 1 AX immW */ -{ "add", 0x05, OP1F, OP_AX, OP_UW, AOT_NONE }, +{ "add", 0x05, OP1F, OP_AX, OP_SW, AOT_NONE }, /* ADD 0x80 /0 ib 1 r/m8 imm8 */ -{ "add", 0x80, OP1F, OP_RM8_D0+0,OP_U8, AOT_NONE }, -{ "add", 0x80, OP1F, OP_RM8_D8+0,OP_U8, AOT_NONE }, -{ "add", 0x80, OP1F, OP_RM8_DW+0,OP_U8, AOT_NONE }, -{ "add", 0x80, OP1F, OP_RM8_R8+0,OP_U8, AOT_NONE }, +{ "add", 0x80, OP1F, OP_RM8_D0+0,OP_S8, AOT_NONE }, +{ "add", 0x80, OP1F, OP_RM8_D8+0,OP_S8, AOT_NONE }, +{ "add", 0x80, OP1F, OP_RM8_DW+0,OP_S8, AOT_NONE }, +{ "add", 0x80, OP1F, OP_RM8_R8+0,OP_S8, AOT_NONE }, /* ADD 0x81 /0 iW 1 r/m8 imm8 */ -{ "add", 0x81, OP1F, OP_RMW_D0+0,OP_UW, AOT_NONE }, -{ "add", 0x81, OP1F, OP_RMW_D8+0,OP_UW, AOT_NONE }, -{ "add", 0x81, OP1F, OP_RMW_DW+0,OP_UW, AOT_NONE }, -{ "add", 0x81, OP1F, OP_RMW_RW+0,OP_UW, AOT_NONE }, +{ "add", 0x81, OP1F, OP_RMW_D0+0,OP_SW, AOT_NONE }, +{ "add", 0x81, OP1F, OP_RMW_D8+0,OP_SW, AOT_NONE }, +{ "add", 0x81, OP1F, OP_RMW_DW+0,OP_SW, AOT_NONE }, +{ "add", 0x81, OP1F, OP_RMW_RW+0,OP_SW, AOT_NONE }, +/* ADD 0x83 /0 i8 1 r/m8 imm8 */ +{ "adc", 0x83, OP1F, OP_RMW_D0+0,OP_S8, AOT_NONE }, +{ "adc", 0x83, OP1F, OP_RMW_D8+0,OP_S8, AOT_NONE }, +{ "adc", 0x83, OP1F, OP_RMW_DW+0,OP_S8, AOT_NONE }, +{ "adc", 0x83, OP1F, OP_RMW_RW+0,OP_S8, AOT_NONE }, /* NOP */ { "nop", 0x90, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },