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Improved support for the Yasep processor some more

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This commit is contained in:
Pierre Pronchery 2011-11-28 03:25:36 +00:00
parent d7b72eaa54
commit 6290fa7746
2 changed files with 58 additions and 0 deletions
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30
src/arch/yasep.ins
View File

@ -42,8 +42,11 @@
{ "and", OPRR(0x02), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "and", OPIRL(0x02),OPIRLF, AO_2(OP_SI4, OP_IMM16) },
{ "and", OPRRL(0x02),OPRRLF, AO_3(OP_SND, OP_SI4, OP_DST3) },
{ "andn", OPIR(0x0a), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "andn", OPRR(0x0a), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "cmps", OPIR(0x1b), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "cmps", OPRR(0x1b), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "cmpu", OPIR(0x13), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "cmpu", OPRR(0x13), OPRRF, AO_2(OP_SI4, OP_SND) },
#if 0 /* XXX aliases */
{ "esb", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
@ -51,43 +54,70 @@
{ "ezb", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "ezh", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
#endif
{ "get", OPIR(0x05), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "get", OPRR(0x05), OPRRF, AO_2(OP_SI4, OP_SND) },
#if 0 /* XXX aliases */
{ "ib", OPIR(0x00), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "ib", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "ih", OPIR(0x00), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "ih", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "ihh", OPIR(0x00), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "ihh", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
#endif
{ "lsb", OPRR(0x18), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "lsh", OPRR(0x38), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "lzb", OPRR(0x10), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "lzh", OPRR(0x30), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "mov", OPIR(0x00), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "mov", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "mul8h", OPIR(0x0c), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "mul8h", OPRR(0x0c), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "mul8l", OPIR(0x04), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "mul8l", OPRR(0x04), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "muli", OPIR(0x14), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "muli", OPRR(0x14), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "nand", OPIR(0x12), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "nand", OPRR(0x12), OPRRF, AO_2(OP_SI4, OP_SND) },
#if 0 /* XXX alias */
{ "neg", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
#endif
{ "nor", OPIR(0x2a), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "nor", OPRR(0x2a), OPRRF, AO_2(OP_SI4, OP_SND) },
#if 0 /* XXX alias */
{ "not", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
#endif
{ "or", OPIR(0x1a), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "or", OPRR(0x1a), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "orn", OPIR(0x22), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "orn", OPRR(0x22), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "put", OPRR(0x0d), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "rol", OPIR(0x21), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "rol", OPRR(0x21), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "ror", OPIR(0x19), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "ror", OPRR(0x19), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "sar", OPIR(0x09), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "sar", OPRR(0x09), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "sb", OPIR(0x08), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "sb", OPRR(0x08), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "sh", OPIR(0x20), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "sh", OPRR(0x20), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "shh", OPIR(0x28), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "shh", OPRR(0x28), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "shl", OPIR(0x11), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "shl", OPRR(0x11), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "shr", OPIR(0x01), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "shr", OPRR(0x01), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "smax", OPIR(0x3b), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "smax", OPRR(0x3b), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "smin", OPIR(0x33), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "smin", OPRR(0x33), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "sub", OPIR(0x0b), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "sub", OPRR(0x0b), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "umax", OPIR(0x2b), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "umax", OPRR(0x2b), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "umin", OPIR(0x23), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "umin", OPRR(0x23), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "xor", OPIR(0x32), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "xor", OPRR(0x32), OPRRF, AO_2(OP_SI4, OP_SND) },
{ "xorn", OPIR(0x3a), OPIRF, AO_2(OP_IMM4, OP_SND) },
{ "xorn", OPRR(0x3a), OPRRF, AO_2(OP_SI4, OP_SND) },

28
test/yasep.S
View File

@ -2,36 +2,64 @@
.text
add $0x0e, %r1
add %r0, %r1
and $0x0d, %r1
and %r2, %r3
andn $0x0c, %r1
andn %r4, %r5
cmps $0x0b, %r1
cmps %r0, %r1
cmpu $0x0a, %r1
cmpu %r0, %r1
get $0x09, %r1
get %r0, %r1
lsb %r0, %r1
lsh %r0, %r1
lzb %r0, %r1
lzh %r0, %r1
mov $0x04, %r1
mov %r0, %r1
mul8h $0x03, %r1
mul8h %r0, %r1
mul8l $0x02, %r1
mul8l %r0, %r1
muli $0x01, %r1
muli %r0, %r1
nand $0x00, %r1
nand %r0, %r1
nor $0x01, %r1
nor %r0, %r1
or $0x02, %r1
or %r0, %r1
orn $0x03, %r1
orn %r0, %r1
put %r0, %r1
rol $0x05, %r1
rol %r0, %r1
ror $0x06, %r1
ror %r0, %r1
sar $0x07, %r1
sar %r0, %r1
sb $0x08, %r1
sb %r0, %r1
sh $0x09, %r1
sh %r0, %r1
shh $0x0a, %r1
shh %r0, %r1
shl $0x0b, %r1
shl %r0, %r1
shr $0x0c, %r1
shr %r0, %r1
smax $0x0d, %r1
smax %r0, %r1
smin $0x0e, %r1
smin %r0, %r1
sub $0x0f, %r1
sub %r0, %r1
umax $0x0e, %r1
umax %r0, %r1
umin $0x0d, %r1
umin %r0, %r1
xor $0x0c, %r1
xor %r0, %r1
xorn $0x0b, %r1
xorn %r0, %r1