Improved support for the Yasep processor some more
This commit is contained in:
parent
d7b72eaa54
commit
6290fa7746
@ -42,8 +42,11 @@
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{ "and", OPRR(0x02), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "and", OPRR(0x02), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "and", OPIRL(0x02),OPIRLF, AO_2(OP_SI4, OP_IMM16) },
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{ "and", OPIRL(0x02),OPIRLF, AO_2(OP_SI4, OP_IMM16) },
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{ "and", OPRRL(0x02),OPRRLF, AO_3(OP_SND, OP_SI4, OP_DST3) },
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{ "and", OPRRL(0x02),OPRRLF, AO_3(OP_SND, OP_SI4, OP_DST3) },
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{ "andn", OPIR(0x0a), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "andn", OPRR(0x0a), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "andn", OPRR(0x0a), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "cmps", OPIR(0x1b), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "cmps", OPRR(0x1b), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "cmps", OPRR(0x1b), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "cmpu", OPIR(0x13), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "cmpu", OPRR(0x13), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "cmpu", OPRR(0x13), OPRRF, AO_2(OP_SI4, OP_SND) },
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#if 0 /* XXX aliases */
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#if 0 /* XXX aliases */
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{ "esb", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "esb", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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@ -51,43 +54,70 @@
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{ "ezb", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "ezb", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "ezh", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "ezh", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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#endif
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#endif
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{ "get", OPIR(0x05), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "get", OPRR(0x05), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "get", OPRR(0x05), OPRRF, AO_2(OP_SI4, OP_SND) },
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#if 0 /* XXX aliases */
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#if 0 /* XXX aliases */
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{ "ib", OPIR(0x00), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "ib", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "ib", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "ih", OPIR(0x00), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "ih", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "ih", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "ihh", OPIR(0x00), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "ihh", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "ihh", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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#endif
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#endif
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{ "lsb", OPRR(0x18), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "lsb", OPRR(0x18), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "lsh", OPRR(0x38), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "lsh", OPRR(0x38), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "lzb", OPRR(0x10), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "lzb", OPRR(0x10), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "lzh", OPRR(0x30), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "lzh", OPRR(0x30), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "mov", OPIR(0x00), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "mov", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "mov", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "mul8h", OPIR(0x0c), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "mul8h", OPRR(0x0c), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "mul8h", OPRR(0x0c), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "mul8l", OPIR(0x04), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "mul8l", OPRR(0x04), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "mul8l", OPRR(0x04), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "muli", OPIR(0x14), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "muli", OPRR(0x14), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "muli", OPRR(0x14), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "nand", OPIR(0x12), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "nand", OPRR(0x12), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "nand", OPRR(0x12), OPRRF, AO_2(OP_SI4, OP_SND) },
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#if 0 /* XXX alias */
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#if 0 /* XXX alias */
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{ "neg", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "neg", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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#endif
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#endif
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{ "nor", OPIR(0x2a), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "nor", OPRR(0x2a), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "nor", OPRR(0x2a), OPRRF, AO_2(OP_SI4, OP_SND) },
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#if 0 /* XXX alias */
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#if 0 /* XXX alias */
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{ "not", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "not", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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#endif
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#endif
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{ "or", OPIR(0x1a), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "or", OPRR(0x1a), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "or", OPRR(0x1a), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "orn", OPIR(0x22), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "orn", OPRR(0x22), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "orn", OPRR(0x22), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "put", OPRR(0x0d), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "put", OPRR(0x0d), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "rol", OPIR(0x21), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "rol", OPRR(0x21), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "rol", OPRR(0x21), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "ror", OPIR(0x19), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "ror", OPRR(0x19), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "ror", OPRR(0x19), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "sar", OPIR(0x09), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "sar", OPRR(0x09), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "sar", OPRR(0x09), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "sb", OPIR(0x08), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "sb", OPRR(0x08), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "sb", OPRR(0x08), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "sh", OPIR(0x20), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "sh", OPRR(0x20), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "sh", OPRR(0x20), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "shh", OPIR(0x28), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "shh", OPRR(0x28), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "shh", OPRR(0x28), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "shl", OPIR(0x11), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "shl", OPRR(0x11), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "shl", OPRR(0x11), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "shr", OPIR(0x01), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "shr", OPRR(0x01), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "shr", OPRR(0x01), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "smax", OPIR(0x3b), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "smax", OPRR(0x3b), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "smax", OPRR(0x3b), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "smin", OPIR(0x33), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "smin", OPRR(0x33), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "smin", OPRR(0x33), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "sub", OPIR(0x0b), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "sub", OPRR(0x0b), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "sub", OPRR(0x0b), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "umax", OPIR(0x2b), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "umax", OPRR(0x2b), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "umax", OPRR(0x2b), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "umin", OPIR(0x23), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "umin", OPRR(0x23), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "umin", OPRR(0x23), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "xor", OPIR(0x32), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "xor", OPRR(0x32), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "xor", OPRR(0x32), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "xorn", OPIR(0x3a), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "xorn", OPRR(0x3a), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "xorn", OPRR(0x3a), OPRRF, AO_2(OP_SI4, OP_SND) },
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28
test/yasep.S
28
test/yasep.S
@ -2,36 +2,64 @@
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.text
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.text
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add $0x0e, %r1
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add $0x0e, %r1
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add %r0, %r1
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add %r0, %r1
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and $0x0d, %r1
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and %r2, %r3
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and %r2, %r3
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andn $0x0c, %r1
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andn %r4, %r5
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andn %r4, %r5
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cmps $0x0b, %r1
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cmps %r0, %r1
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cmps %r0, %r1
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cmpu $0x0a, %r1
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cmpu %r0, %r1
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cmpu %r0, %r1
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get $0x09, %r1
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get %r0, %r1
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get %r0, %r1
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lsb %r0, %r1
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lsb %r0, %r1
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lsh %r0, %r1
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lsh %r0, %r1
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lzb %r0, %r1
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lzb %r0, %r1
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lzh %r0, %r1
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lzh %r0, %r1
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mov $0x04, %r1
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mov %r0, %r1
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mov %r0, %r1
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mul8h $0x03, %r1
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mul8h %r0, %r1
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mul8h %r0, %r1
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mul8l $0x02, %r1
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mul8l %r0, %r1
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mul8l %r0, %r1
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muli $0x01, %r1
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muli %r0, %r1
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muli %r0, %r1
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nand $0x00, %r1
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nand %r0, %r1
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nand %r0, %r1
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nor $0x01, %r1
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nor %r0, %r1
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nor %r0, %r1
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or $0x02, %r1
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or %r0, %r1
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or %r0, %r1
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orn $0x03, %r1
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orn %r0, %r1
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orn %r0, %r1
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put %r0, %r1
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put %r0, %r1
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rol $0x05, %r1
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rol %r0, %r1
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rol %r0, %r1
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ror $0x06, %r1
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ror %r0, %r1
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ror %r0, %r1
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sar $0x07, %r1
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sar %r0, %r1
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sar %r0, %r1
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sb $0x08, %r1
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sb %r0, %r1
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sb %r0, %r1
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sh $0x09, %r1
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sh %r0, %r1
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sh %r0, %r1
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shh $0x0a, %r1
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shh %r0, %r1
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shh %r0, %r1
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shl $0x0b, %r1
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shl %r0, %r1
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shl %r0, %r1
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shr $0x0c, %r1
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shr %r0, %r1
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shr %r0, %r1
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smax $0x0d, %r1
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smax %r0, %r1
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smax %r0, %r1
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smin $0x0e, %r1
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smin %r0, %r1
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smin %r0, %r1
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sub $0x0f, %r1
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sub %r0, %r1
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sub %r0, %r1
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umax $0x0e, %r1
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umax %r0, %r1
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umax %r0, %r1
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umin $0x0d, %r1
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umin %r0, %r1
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umin %r0, %r1
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xor $0x0c, %r1
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xor %r0, %r1
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xor %r0, %r1
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xorn $0x0b, %r1
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xorn %r0, %r1
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xorn %r0, %r1
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