diff --git a/src/arch/yasep.ins b/src/arch/yasep.ins
index 6d10535..454fc88 100644
--- a/src/arch/yasep.ins
+++ b/src/arch/yasep.ins
@@ -27,11 +27,11 @@
 #define OPIRLF		(32 << AOD_SIZE)
 #define OPRRLF		(32 << AOD_SIZE)
 /* operands */
-#define OP_DST3		AO_REGISTER(0, 32, 0)
+#define OP_DST3		AO_REGISTER(0, 16, 0)
 #define OP_IMM4		AO_IMMEDIATE(0, 4, 0)
 #define OP_IMM16	AO_IMMEDIATE(0, 16, 0)
-#define OP_SI4		AO_REGISTER(0, 32, 0)
-#define OP_SND		AO_REGISTER(0, 32, 0)
+#define OP_SI4		AO_REGISTER(0, 16, 0)
+#define OP_SND		AO_REGISTER(0, 16, 0)
 
 /* instructions */
 { "add",	OPIR(0x03), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
diff --git a/src/arch/yasep.reg b/src/arch/yasep.reg
index 3db9272..b190c37 100644
--- a/src/arch/yasep.reg
+++ b/src/arch/yasep.reg
@@ -1,16 +1,16 @@
-REG(r0,  32, 0x00)
-REG(r1,  32, 0x01)
-REG(r2,  32, 0x02)
-REG(r3,  32, 0x03)
-REG(r4,  32, 0x04)
-REG(r5,  32, 0x05)
-REG(r6,  32, 0x06)
-REG(r7,  32, 0x07)
-REG(r8,  32, 0x08)
-REG(r9,  32, 0x09)
-REG(r10, 32, 0x0a)
-REG(r11, 32, 0x0b)
-REG(r12, 32, 0x0c)
-REG(r13, 32, 0x0d)
-REG(r14, 32, 0x0e)
-REG(r15, 32, 0x0f)
+REG(r0,  16, 0x00)
+REG(r1,  16, 0x01)
+REG(r2,  16, 0x02)
+REG(r3,  16, 0x03)
+REG(r4,  16, 0x04)
+REG(r5,  16, 0x05)
+REG(r6,  16, 0x06)
+REG(r7,  16, 0x07)
+REG(r8,  16, 0x08)
+REG(r9,  16, 0x09)
+REG(r10, 16, 0x0a)
+REG(r11, 16, 0x0b)
+REG(r12, 16, 0x0c)
+REG(r13, 16, 0x0d)
+REG(r14, 16, 0x0e)
+REG(r15, 16, 0x0f)