From 8973221291515458fa0ef6fef5e0b951b2431ef0 Mon Sep 17 00:00:00 2001 From: Pierre Pronchery Date: Mon, 18 Apr 2011 06:30:43 +0000 Subject: [PATCH] Added the "shrd" instruction (doesn't seem to work) --- src/arch/i386.ins | 19 +++++++++++++++++++ test/i386.S | 4 ++++ 2 files changed, 23 insertions(+) diff --git a/src/arch/i386.ins b/src/arch/i386.ins index 055dd39..215af16 100644 --- a/src/arch/i386.ins +++ b/src/arch/i386.ins @@ -50,6 +50,7 @@ #define OP_R8 AO_REGISTER(0, 8, 0) #define OP_RW AO_REGISTER(0, W, 0) #define OP_al AO_REGISTER(AOF_IMPLICIT, REG_al_size, REG_al_id) +#define OP_cl AO_REGISTER(AOF_IMPLICIT, REG_cl_size, REG_cl_id) #define OP_AX AO_REGISTER(AOF_IMPLICIT, W, REG_AX_id) #define OP_CX AO_REGISTER(AOF_IMPLICIT, W, REG_CX_id) #define OP_DX AO_REGISTER(AOF_IMPLICIT, W, REG_DX_id) @@ -420,6 +421,24 @@ { "fwait", 0x9b, OP1F, AOT_NONE, AOT_NONE, AOT_NONE }, /* NOP 0x90 1 */ { "nop", 0x90, OP1F, AOT_NONE, AOT_NONE, AOT_NONE }, +/* SHRD 0x0fac 2 r/mW rW imm8 */ +#if 1 /* FIXME doesn't work */ +{ "shrd", 0x0fac, OP2F, OP_RMW_D0, OP_RW, OP_U8 }, +{ "shrd", 0x0fac, OP2F, OP_RMW_D8, OP_RW, OP_U8 }, +{ "shrd", 0x0fac, OP2F, OP_RMW_DW, OP_RW, OP_U8 }, +{ "shrd", 0x0fac, OP2F, OP_RMW_RW, OP_RW, OP_U8 }, +#endif +/* SHRD 0x0fad 2 r/mW rW cl */ +#if 1 /* FIXME doesn't work */ +{ "shrd", 0x0fad, OP2F, OP_RMW_D0, OP_RW, OP_cl }, +{ "shrd", 0x0fad, OP2F, OP_RMW_D8, OP_RW, OP_cl }, +{ "shrd", 0x0fad, OP2F, OP_RMW_DW, OP_RW, OP_cl }, +{ "shrd", 0x0fad, OP2F, OP_RMW_RW, OP_RW, OP_cl }, +#endif +/* SLDT 0x0f00 /0 2 r/mW */ +/* FIXME implement */ +/* SMSW 0x0f01 /4 2 r/mW */ +/* FIXME implement */ /* STC 0xf9 */ { "stc", 0xf9, OP1F, AOT_NONE, AOT_NONE, AOT_NONE }, /* STD 0xfd */ diff --git a/test/i386.S b/test/i386.S index e358719..f47b4ee 100644 --- a/test/i386.S +++ b/test/i386.S @@ -146,6 +146,10 @@ fnclex fwait nop /* 90 */ +#if 0 /* FIXME doesn't work */ + shrd %eax, %eax, $0x31 + shrd %eax, %eax, %cl +#endif stc std sti