Improving ARM support
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221bad8794
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@ -88,16 +88,16 @@ static int _arm_write(ArchPlugin * plugin, ArchInstruction * instruction,
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case rsc | (0x1 << 25):
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case rsc | (0x1 << 25):
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case orr | (0x1 << 25):
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case orr | (0x1 << 25):
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case bic | (0x1 << 25):
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case bic | (0x1 << 25):
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case and | (0x1 << 20) | (0x1 << 25):
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case and | (0x1 << 25) | (0x1 << 20): /* ands (immediate) */
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case eor | (0x1 << 20) | (0x1 << 25):
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case eor | (0x1 << 25) | (0x1 << 20): /* eors (immediate) */
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case sub | (0x1 << 20) | (0x1 << 25):
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case sub | (0x1 << 25) | (0x1 << 20): /* subs (immediate) */
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case rsb | (0x1 << 20) | (0x1 << 25):
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case rsb | (0x1 << 25) | (0x1 << 20): /* rsbs (immediate) */
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case add | (0x1 << 20) | (0x1 << 25):
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case add | (0x1 << 25) | (0x1 << 20): /* adds (immediate) */
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case adc | (0x1 << 20) | (0x1 << 25):
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case adc | (0x1 << 25) | (0x1 << 20): /* adcs (immediate) */
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case sbc | (0x1 << 20) | (0x1 << 25):
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case sbc | (0x1 << 25) | (0x1 << 20): /* sbcs (immediate) */
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case rsc | (0x1 << 20) | (0x1 << 25):
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case rsc | (0x1 << 25) | (0x1 << 20): /* rscs (immediate) */
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case orr | (0x1 << 20) | (0x1 << 25):
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case orr | (0x1 << 25) | (0x1 << 20): /* orrs (immediate) */
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case bic | (0x1 << 20) | (0x1 << 25):
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case bic | (0x1 << 25) | (0x1 << 20): /* bics (immediate) */
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/* first operand, Rd */
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/* first operand, Rd */
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p = call->operands[0].value._register.name;
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p = call->operands[0].value._register.name;
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if((ar = helper->get_register_by_name_size(helper->arch,
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if((ar = helper->get_register_by_name_size(helper->arch,
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@ -113,13 +113,44 @@ static int _arm_write(ArchPlugin * plugin, ArchInstruction * instruction,
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/* third operand */
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/* third operand */
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opcode |= call->operands[2].value.immediate.value;
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opcode |= call->operands[2].value.immediate.value;
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break;
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break;
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#if 1 /* FIXME implement */
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case tst:
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case tst:
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case teq:
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case teq:
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case cmp:
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case cmp:
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case cmn:
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case cmn:
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case tst | (0x1 << 20): /* tsts */
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case teq | (0x1 << 20): /* teqs */
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case cmp | (0x1 << 20): /* cmps */
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case cmn | (0x1 << 20): /* cmns */
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/* first operand, Rn */
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p = call->operands[0].value._register.name;
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if((ar = helper->get_register_by_name_size(helper->arch,
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p, 32)) == NULL)
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return -1;
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opcode |= (ar->id << 16);
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/* second operand, Rm */
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p = call->operands[1].value._register.name;
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if((ar = helper->get_register_by_name_size(helper->arch,
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p, 32)) == NULL)
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return -1;
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opcode |= ar->id;
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break;
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case tst | (0x1 << 25):
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case teq | (0x1 << 25):
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case cmp | (0x1 << 25):
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case cmn | (0x1 << 25):
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case tst | (0x1 << 25) | (0x1 << 20): /* tsts (immediate) */
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case teq | (0x1 << 25) | (0x1 << 20): /* teqs (immediate) */
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case cmp | (0x1 << 25) | (0x1 << 20): /* cmps (immediate) */
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case cmn | (0x1 << 25) | (0x1 << 20): /* cmns (immediate) */
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/* first operand, Rn */
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p = call->operands[0].value._register.name;
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if((ar = helper->get_register_by_name_size(helper->arch,
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p, 32)) == NULL)
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return -1;
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opcode |= (ar->id << 16);
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/* second operand */
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opcode |= call->operands[1].value.immediate.value;
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break;
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break;
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#endif
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case mov:
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case mov:
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case mov | (0x1 << 20): /* movs */
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case mov | (0x1 << 20): /* movs */
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case mvn:
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case mvn:
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