diff --git a/src/arch/arm.c b/src/arch/arm.c index 4486cb9..dc94435 100644 --- a/src/arch/arm.c +++ b/src/arch/arm.c @@ -1,5 +1,5 @@ /* $Id$ */ -/* Copyright (c) 2011 Pierre Pronchery */ +/* Copyright (c) 2011-2012 Pierre Pronchery */ /* This file is part of DeforaOS Devel asm */ /* This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -77,5 +77,5 @@ AsmArchPlugin arch_plugin = NULL, NULL, _arm_encode, - NULL + _arm_decode }; diff --git a/src/arch/arm.h b/src/arch/arm.h index 0f1745c..40f225e 100644 --- a/src/arch/arm.h +++ b/src/arch/arm.h @@ -22,12 +22,243 @@ /* private */ /* prototypes */ /* plug-in */ +static int _arm_decode(AsmArchPlugin * plugin, AsmArchInstructionCall * call); static int _arm_encode(AsmArchPlugin * plugin, AsmArchInstruction * instruction, AsmArchInstructionCall * call); /* functions */ /* plug-in */ +/* arm_decode */ +static void _decode_reg_reg_dreg(AsmArchPlugin * plugin, + AsmArchInstructionCall * call, uint32_t opcode); +static void _decode_reg_reg_reg(AsmArchPlugin * plugin, + AsmArchInstructionCall * call, uint32_t opcode); +static void _decode_reg_reg_u12(AsmArchPlugin * plugin, + AsmArchInstructionCall * call, uint32_t opcode); +static void _decode_u24(AsmArchInstructionCall * call, uint32_t opcode); +static void _decode_u4_u4_reg(AsmArchPlugin * plugin, + AsmArchInstructionCall * call, uint32_t opcode); +static int _decode_unknown(AsmArchInstructionCall * call, uint32_t opcode); + +static int _arm_decode(AsmArchPlugin * plugin, AsmArchInstructionCall * call) +{ + AsmArchPluginHelper * helper = plugin->helper; + uint32_t opcode; + uint32_t op; + AsmArchInstruction * ai; + + /* read 4 bytes in the proper endian */ + if(helper->read(helper->arch, &opcode, sizeof(opcode)) + != sizeof(opcode)) + return -1; +#if 1 + /* FIXME apply as relevant */ + opcode = _htob32(opcode); +#endif + /* lookup the instruction */ + /* FIXME decode everything in the proper order */ + /* bits 27, 26, 25 and 24 are set */ + if((op = (opcode & OPSI(0x0))) == OPSI(0x0)) + { + ai = helper->get_instruction_by_opcode(helper->arch, 32, + opcode & OPSI(0xf)); + _decode_u24(call, opcode); + } + /* bits 27, 26, 25 are set */ + else if((op = (opcode & OPCDO(0x0))) == OPCDO(0x0)) + { + ai = helper->get_instruction_by_opcode(helper->arch, 32, + opcode & OPCDO(0xf)); + _decode_u4_u4_reg(plugin, call, opcode); + } + /* bits 27, 25, 24 are set */ + else if((op = (opcode & OPBL(0x0))) == OPBL(0x0)) + ai = helper->get_instruction_by_opcode(helper->arch, 32, + opcode & OPBL(0xf)); + /* bits 27, 25 are set */ + else if((op = (opcode & OPB(0x0))) == OPB(0x0)) + ai = helper->get_instruction_by_opcode(helper->arch, 32, + opcode & OPB(0xf)); + /* bits 26, 25, 22, 20 */ + else if((op = (opcode & OPSDTLB(0x0))) == OPSDTLB(0x0)) + ai = helper->get_instruction_by_opcode(helper->arch, 32, + opcode & OPSDTLB(0xf)); + /* bits 26, 25, 22 are set */ + else if((op = (opcode & OPSDTSB(0x0))) == OPSDTSB(0x0)) + ai = helper->get_instruction_by_opcode(helper->arch, 32, + opcode & OPSDTSB(0xf)); + /* bits 26, 25, 20 are set */ + else if((op = (opcode & OPSDTL(0x0))) == OPSDTL(0x0)) + ai = helper->get_instruction_by_opcode(helper->arch, 32, + opcode & OPSDTL(0xf)); + /* bits 26, 25 are set */ + else if((op = (opcode & OPSDTS(0x0))) == OPSDTS(0x0)) + ai = helper->get_instruction_by_opcode(helper->arch, 32, + opcode & OPSDTS(0xf)); + /* bits 25, 20 are set */ + else if((op = (opcode & OPDPIS(0x0, 0x0))) == OPDPIS(0x0, 0x0)) + { + ai = helper->get_instruction_by_opcode(helper->arch, 32, + opcode & OPDPIS(0xf, 0xf)); + _decode_reg_reg_u12(plugin, call, opcode); + } + /* bit 25 is set */ + else if((op = (opcode & OPDPI(0x0, 0x0))) == OPDPI(0x0, 0x0)) + { + ai = helper->get_instruction_by_opcode(helper->arch, 32, + opcode & OPDPI(0xf, 0xf)); + _decode_reg_reg_u12(plugin, call, opcode); + } + /* bits 24, 22 are set */ + else if((op = (opcode & OPSDSB(0x0))) == OPSDSB(0x0)) + { + ai = helper->get_instruction_by_opcode(helper->arch, 32, + opcode & OPSDSB(0xf)); + _decode_reg_reg_dreg(plugin, call, opcode); + } + /* bit 24 is set */ + else if((op = (opcode & OPPTI(0x0))) == OPPTI(0x0)) + ai = helper->get_instruction_by_opcode(helper->arch, 32, + opcode & OPPTI(0xf)); + /* bit 24 is set */ + else if((op = (opcode & OPPT(0x0))) == OPPT(0x0)) + ai = helper->get_instruction_by_opcode(helper->arch, 32, + opcode & OPPT(0xf)); + /* bit 24 is set */ + else if((op = (opcode & OPSDS(0x0))) == OPSDS(0x0)) + { + ai = helper->get_instruction_by_opcode(helper->arch, 32, + opcode & OPSDS(0xf)); + _decode_reg_reg_dreg(plugin, call, opcode); + } + /* bits 21, 20, 8 and 4 are set */ + else if((op = (opcode & OPMULAS(0x0))) == OPMULAS(0x0)) + ai = helper->get_instruction_by_opcode(helper->arch, 32, + opcode & OPMULAS(0xf)); + /* bits 4, 5, 6, 7, 8, 9, 10, 12, 12, 13, 14, 15, 16, 18, 21 are set */ + else if((op = (opcode & OPBX(0x0))) == OPBX(0x0)) + ai = helper->get_instruction_by_opcode(helper->arch, 32, + opcode & OPBX(0xf)); + /* bits 21, 8 and 4 are set */ + else if((op = (opcode & OPMULA(0x0))) == OPMULA(0x0)) + ai = helper->get_instruction_by_opcode(helper->arch, 32, + opcode & OPMULA(0xf)); + /* bits 20, 8 and 4 are set */ + else if((op = (opcode & OPMULS(0x0))) == OPMULS(0x0)) + ai = helper->get_instruction_by_opcode(helper->arch, 32, + opcode & OPMULS(0xf)); + /* bit 20 is set */ + else if((op = (opcode & OPDPS(0x0, 0x0))) == OPDPS(0x0, 0x0)) + { + ai = helper->get_instruction_by_opcode(helper->arch, 32, + opcode & OPDPS(0xf, 0xf)); + _decode_reg_reg_reg(plugin, call, opcode); + } + /* bits 8 and 4 are set */ + else if((op = (opcode & OPMUL(0x0))) == OPMUL(0x0)) + { + ai = helper->get_instruction_by_opcode(helper->arch, 32, + opcode & OPMUL(0xf)); + _decode_reg_reg_reg(plugin, call, opcode); + } + /* no bits set */ + else if((op = (opcode & OPDP(0x0, 0x0))) == OPDP(0x0, 0x0)) + { + ai = helper->get_instruction_by_opcode(helper->arch, 32, + opcode & OPDP(0xf, 0xf)); + _decode_reg_reg_reg(plugin, call, opcode); + } + else + /* unknown instruction */ + return _decode_unknown(call, opcode); + call->name = ai->name; + call->operands_cnt = 0; + if((call->operands[0].definition = ai->op1) != AOT_NONE) + call->operands_cnt++; + if((call->operands[1].definition = ai->op2) != AOT_NONE) + call->operands_cnt++; + if((call->operands[2].definition = ai->op3) != AOT_NONE) + call->operands_cnt++; + return 0; +} + +static void _decode_reg_reg_dreg(AsmArchPlugin * plugin, + AsmArchInstructionCall * call, uint32_t opcode) +{ + AsmArchPluginHelper * helper = plugin->helper; + AsmArchRegister * ar; + + if((ar = helper->get_register_by_id_size(helper->arch, + (opcode >> 12) & 0xf, 32)) != NULL) + call->operands[0].value._register.name = ar->name; + if((ar = helper->get_register_by_id_size(helper->arch, + (opcode >> 16) & 0xf, 32)) != NULL) + call->operands[1].value._register.name = ar->name; + if((ar = helper->get_register_by_id_size(helper->arch, + opcode & 0xf, 32)) != NULL) + call->operands[2].value.dregister.name = ar->name; +} + +static void _decode_reg_reg_reg(AsmArchPlugin * plugin, + AsmArchInstructionCall * call, uint32_t opcode) +{ + AsmArchPluginHelper * helper = plugin->helper; + AsmArchRegister * ar; + + if((ar = helper->get_register_by_id_size(helper->arch, + (opcode >> 12) & 0xf, 32)) != NULL) + call->operands[0].value._register.name = ar->name; + if((ar = helper->get_register_by_id_size(helper->arch, + (opcode >> 16) & 0xf, 32)) != NULL) + call->operands[1].value._register.name = ar->name; + if((ar = helper->get_register_by_id_size(helper->arch, + opcode & 0xf, 32)) != NULL) + call->operands[2].value._register.name = ar->name; +} + +static void _decode_reg_reg_u12(AsmArchPlugin * plugin, + AsmArchInstructionCall * call, uint32_t opcode) +{ + AsmArchPluginHelper * helper = plugin->helper; + AsmArchRegister * ar; + + if((ar = helper->get_register_by_id_size(helper->arch, + (opcode >> 12) & 0xf, 32)) != NULL) + call->operands[0].value._register.name = ar->name; + if((ar = helper->get_register_by_id_size(helper->arch, + (opcode >> 16) & 0xf, 32)) != NULL) + call->operands[1].value._register.name = ar->name; + call->operands[2].value.immediate.value = opcode & 0xfff; +} + +static void _decode_u24(AsmArchInstructionCall * call, uint32_t opcode) +{ + call->operands[0].value.immediate.value = opcode & 0x00ffffff; +} + +static void _decode_u4_u4_reg(AsmArchPlugin * plugin, + AsmArchInstructionCall * call, uint32_t opcode) +{ + AsmArchPluginHelper * helper = plugin->helper; + AsmArchRegister * ar; + + /* FIXME implement u4 and u4 */ + if((ar = helper->get_register_by_id_size(helper->arch, + (opcode >> 12) & 0xf, 32)) != NULL) + call->operands[2].value._register.name = ar->name; +} + +static int _decode_unknown(AsmArchInstructionCall * call, uint32_t opcode) +{ + call->name = "dw"; + call->operands[0].definition = AO_IMMEDIATE(0, 32, 0); + call->operands[0].value.immediate.value = opcode; + call->operands_cnt = 1; + return 0; +} + + /* arm_encode */ static int _arm_encode(AsmArchPlugin * plugin, AsmArchInstruction * instruction, AsmArchInstructionCall * call) @@ -37,7 +268,7 @@ static int _arm_encode(AsmArchPlugin * plugin, AsmArchInstruction * instruction, AsmArchRegister * ar; char const * p; - switch(instruction->opcode & 0x0fffffff) /* ignore condition code */ + switch(opcode & 0x0fffffff) /* ignore condition code */ { /* branch, branch with link */ case OPB(0): /* b */ @@ -356,6 +587,10 @@ static int _arm_encode(AsmArchPlugin * plugin, AsmArchInstruction * instruction, break; #endif } +#if 1 + /* FIXME apply as relevant */ + opcode = _htob32(opcode); +#endif if(helper->write(helper->arch, &opcode, sizeof(opcode)) != sizeof(opcode)) return -1; diff --git a/src/arch/arm.ins b/src/arch/arm.ins index 96240c3..9387274 100644 --- a/src/arch/arm.ins +++ b/src/arch/arm.ins @@ -17,21 +17,21 @@ /* generic */ /* conditions */ -#define eq (0x0 << 28) -#define ne (0x1 << 28) -#define cs (0x2 << 28) -#define cc (0x3 << 28) -#define mi (0x4 << 28) -#define pl (0x5 << 28) -#define vs (0x6 << 28) -#define vc (0x7 << 28) -#define hi (0x8 << 28) -#define ls (0x9 << 28) -#define ge (0xa << 28) -#define lt (0xb << 28) -#define gt (0xc << 28) -#define le (0xd << 28) -#define al (0xe << 28) +#define eq 0x0 +#define ne 0x1 +#define cs 0x2 +#define cc 0x3 +#define mi 0x4 +#define pl 0x5 +#define vs 0x6 +#define vc 0x7 +#define hi 0x8 +#define ls 0x9 +#define ge 0xa +#define lt 0xb +#define gt 0xc +#define le 0xd +#define al 0xe /* opcodes */ #define OPNOP AO_IMMEDIATE(0, 32, 0) @@ -41,114 +41,114 @@ #define OP_R_SPSR AO_REGISTER(AOF_IMPLICIT, 32, REG_spsr_id) /* block data transfer */ -#define OPBDTL(cond) (cond | (0x4 << 25) | (0x1 << 20)) +#define OPBDTL(cond) ((cond << 28) | (0x4 << 25) | (0x1 << 20)) #define OPBDTLF (32 << AOD_SIZE) #define OPBDT_U16 AO_IMMEDIATE(0, 16, 0) -#define OPBDTS(cond) (cond | (0x4 << 25)) +#define OPBDTS(cond) ((cond << 28) | (0x4 << 25)) #define OPBDTSF (32 << AOD_SIZE) /* branch, branch with link */ -#define OPB(cond) (cond | (0x5 << 25)) +#define OPB(cond) ((cond << 28) | (0x5 << 25)) #define OPBF (32 << AOD_SIZE) #define OPB_S26 AO_IMMEDIATE(AOF_SIGNED, 26, 0) -#define OPBL(cond) (cond | (0x5 << 25) | (0x1 << 24)) +#define OPBL(cond) ((cond << 28) | (0x5 << 25) | (0x1 << 24)) #define OPBLF (32 << AOD_SIZE) #define OPBL_S26 AO_IMMEDIATE(AOF_SIGNED, 26, 0) /* branch and exchange */ -#define OPBX(cond) (cond | (0x12fff1 << 4)) +#define OPBX(cond) ((cond << 28) | (0x12fff1 << 4)) #define OPBXF (32 << AOD_SIZE) /* coprocessor data operation */ -#define OPCDO(cond) (cond | (0xe << 24)) +#define OPCDO(cond) ((cond << 28) | (0xe << 24)) #define OPCDOF (32 << AOD_SIZE) #define OPCDO_U4 AO_IMMEDIATE(0, 4, 0) /* coprocessor data transfers */ -#define OPCDTL(cond) (cond | (0x6 << 25) | (0x1 << 20)) +#define OPCDTL(cond) ((cond << 28) | (0x6 << 25) | (0x1 << 20)) #define OPCDTLF (32 << AOD_SIZE) #define OPCDTL_U4 AO_IMMEDIATE(0, 4, 0) #define OPCDTL_U8 AO_IMMEDIATE(0, 8, 0) -#define OPCDTS(cond) (cond | (0x6 << 25)) +#define OPCDTS(cond) ((cond << 28) | (0x6 << 25)) #define OPCDTSF (32 << AOD_SIZE) #define OPCDTS_U4 AO_IMMEDIATE(0, 4, 0) #define OPCDTS_U8 AO_IMMEDIATE(0, 8, 0) /* coprocessor register transfers */ -#define OPCRTL(cond) (cond | (0xe << 24) | (0x1 << 20) | (0x1 << 4)) +#define OPCRTL(cond) ((cond << 28) | (0xe << 24) | (0x1 << 20) | (0x1 << 4)) #define OPCRTLF (32 << AOD_SIZE) #define OPCRTL_U3 AO_IMMEDIATE(0, 3, 0) #define OPCRTL_U4 AO_IMMEDIATE(0, 4, 0) -#define OPCRTS(cond) (cond | (0xe << 24) | (0x1 << 4)) +#define OPCRTS(cond) ((cond << 28) | (0xe << 24) | (0x1 << 4)) #define OPCRTSF (32 << AOD_SIZE) #define OPCRTS_U3 AO_IMMEDIATE(0, 3, 0) #define OPCRTS_U4 AO_IMMEDIATE(0, 4, 0) /* data processing */ /* operations */ -#define and (0x0 << 21) -#define eor (0x1 << 21) -#define sub (0x2 << 21) -#define rsb (0x3 << 21) -#define add (0x4 << 21) -#define adc (0x5 << 21) -#define sbc (0x6 << 21) -#define rsc (0x7 << 21) -#define tst (0x8 << 21) -#define teq (0x9 << 21) -#define cmp (0xa << 21) -#define cmn (0xb << 21) -#define orr (0xc << 21) -#define mov (0xd << 21) -#define bic (0xe << 21) -#define mvn (0xf << 21) +#define and 0x0 +#define eor 0x1 +#define sub 0x2 +#define rsb 0x3 +#define add 0x4 +#define adc 0x5 +#define sbc 0x6 +#define rsc 0x7 +#define tst 0x8 +#define teq 0x9 +#define cmp 0xa +#define cmn 0xb +#define orr 0xc +#define mov 0xd +#define bic 0xe +#define mvn 0xf -#define OPDP(cond, op) (cond | op) +#define OPDP(cond, op) ((cond << 28) | (op << 21)) #define OPDPF (32 << AOD_SIZE) -#define OPDPI(cond, op) (cond | op | (0x1 << 25)) +#define OPDPI(cond, op) ((cond << 28) | (op << 21) | (0x1 << 25)) #define OPDPIF (32 << AOD_SIZE) #define OPDPI_U12 AO_IMMEDIATE(0, 12, 0) -#define OPDPS(cond, op) (cond | op | (0x1 << 20)) +#define OPDPS(cond, op) ((cond << 28) | (op << 21) | (0x1 << 20)) #define OPDPSF (32 << AOD_SIZE) -#define OPDPIS(cond, op)(cond | op | (0x1 << 25) | (0x1 << 20)) +#define OPDPIS(cond, op)((cond << 28) | (op << 21) | (0x1 << 25) | (0x1 << 20)) #define OPDPISF (32 << AOD_SIZE) #define OPDPIS_U12 OPDPI_U12 /* multiply and multiply-accumulate */ -#define OPMUL(cond) (cond | (0x9 << 4)) +#define OPMUL(cond) ((cond << 28) | (0x9 << 4)) #define OPMULF (32 << AOD_SIZE) -#define OPMULS(cond) (cond | (0x1 << 20) | (0x9 << 4)) +#define OPMULS(cond) ((cond << 28) | (0x1 << 20) | (0x9 << 4)) #define OPMULSF (32 << AOD_SIZE) -#define OPMULA(cond) (cond | (0x1 << 21) | (0x9 << 4)) +#define OPMULA(cond) ((cond << 28) | (0x1 << 21) | (0x9 << 4)) #define OPMULAF (32 << AOD_SIZE) -#define OPMULAS(cond) (cond | (0x1 << 21) | (0x1 << 20) | (0x9 << 4)) +#define OPMULAS(cond) ((cond << 28) | (0x1 << 21) | (0x1 << 20) | (0x9 << 4)) #define OPMULASF (32 << AOD_SIZE) /* psr transfer */ -#define OPPT(cond) (cond | (0x2 << 23) | (0xf << 16)) +#define OPPT(cond) ((cond << 28) | (0x2 << 23) | (0xf << 16)) #define OPPTF (32 << AOD_SIZE) -#define OPPTI(cond) (cond | (0x2 << 23) | (0x29f << 12)) +#define OPPTI(cond) ((cond << 28) | (0x2 << 23) | (0x29f << 12)) #define OPPTIF (32 << AOD_SIZE) /* single data transfer */ -#define OPSDTL(cond) (cond | (0x1 << 26) | (0x1 << 25) | (0x1 << 20)) +#define OPSDTL(cond) ((cond << 28) | (0x1 << 26) | (0x1 << 25) | (0x1 << 20)) #define OPSDTLF (32 << AOD_SIZE) -#define OPSDTS(cond) (cond | (0x1 << 26) | (0x1 << 25)) +#define OPSDTS(cond) ((cond << 28) | (0x1 << 26) | (0x1 << 25)) #define OPSDTSF (32 << AOD_SIZE) -#define OPSDTLB(cond) (cond | (0x1 << 26) | (0x1 << 25) | (0x1 << 22) \ - | (0x1 << 20)) +#define OPSDTLB(cond) ((cond << 28) | (0x1 << 26) | (0x1 << 25) \ + | (0x1 << 22) | (0x1 << 20)) #define OPSDTLBF (32 << AOD_SIZE) -#define OPSDTSB(cond) (cond | (0x1 << 26) | (0x1 << 25) | (0x1 << 22)) +#define OPSDTSB(cond) ((cond << 28) | (0x1 << 26) | (0x1 << 25) | (0x1 << 22)) #define OPSDTSBF (32 << AOD_SIZE) /* single data swap */ -#define OPSDS(cond) (cond | (0x2 << 23) | (0x9 << 4)) +#define OPSDS(cond) ((cond << 28) | (0x2 << 23) | (0x9 << 4)) #define OPSDSF (32 << AOD_SIZE) -#define OPSDSB(cond) (cond | (0x2 << 23) | (0x1 << 22) | (0x9 << 4)) +#define OPSDSB(cond) ((cond << 28) | (0x2 << 23) | (0x1 << 22) | (0x9 << 4)) #define OPSDSBF (32 << AOD_SIZE) /* software interrupt */ -#define OPSI(cond) (cond | (0xf << 24)) +#define OPSI(cond) ((cond << 28) | (0xf << 24)) #define OPSIF (32 << AOD_SIZE) #define OPSI_U24 AO_IMMEDIATE(0, 24, 0) diff --git a/tests/Makefile b/tests/Makefile index c30274f..3dcc9cd 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -72,13 +72,13 @@ yasep32.o_ASFLAGS = $(CPPFLAGSF) $(CPPFLAGS) $(ASFLAGS) -a yasep32 -f flat amd64.o: amd64.asm ../src/asm $(AS) $(amd64.o_ASFLAGS) -o amd64.o amd64.asm -arm.o: arm.asm ../src/asm +arm.o: arm.asm ../src/arch/arm.so ../src/asm $(AS) $(arm.o_ASFLAGS) -o arm.o arm.asm -armeb.o: armeb.asm arm.asm ../src/asm +armeb.o: armeb.asm ../src/arch/armeb.so arm.asm ../src/asm $(AS) $(armeb.o_ASFLAGS) -o armeb.o armeb.asm -armel.o: armel.asm arm.asm ../src/asm +armel.o: armel.asm ../src/arch/armel.so arm.asm ../src/asm $(AS) $(armel.o_ASFLAGS) -o armel.o armel.asm dalvik.o: dalvik.asm ../src/asm diff --git a/tests/arm.asm b/tests/arm.asm index 9cf661b..95a267a 100644 --- a/tests/arm.asm +++ b/tests/arm.asm @@ -2,8 +2,34 @@ .text adc %r3, %r4, %r5 adceq %r3, %r4, %r5 + adcne %r3, %r4, %r5 + adccs %r3, %r4, %r5 + adccc %r3, %r4, %r5 + adcmi %r3, %r4, %r5 + adcpl %r3, %r4, %r5 + adcvs %r3, %r4, %r5 + adcvc %r3, %r4, %r5 + adchi %r3, %r4, %r5 + adcls %r3, %r4, %r5 + adcge %r3, %r4, %r5 + adclt %r3, %r4, %r5 + adcgt %r3, %r4, %r5 + adcle %r3, %r4, %r5 + adcal %r3, %r4, %r5 adc %r4, %r5, $0x0 adceq %r4, %r5, $0x1 + adcne %r4, %r5, $0x2 + adccc %r4, %r5, $0x3 + adcpl %r4, %r5, $0x4 + adcvs %r4, %r5, $0x5 + adcvc %r4, %r5, $0x6 + adchi %r4, %r5, $0x7 + adcls %r4, %r5, $0x8 + adcge %r4, %r5, $0x9 + adclt %r4, %r5, $0xa + adcgt %r4, %r5, $0xb + adcle %r4, %r5, $0xc + adcal %r4, %r5, $0xd adcs %r3, %r4, %r5 adceqs %r3, %r4, %r5 adcs %r3, %r4, $0x0 @@ -38,8 +64,8 @@ bleq $0xa0 bx %r1 bxeq %r2 - cdp $0x1, $0xf, %r0 - cdpeq $0x2, $0xe, %r0 + cdp $0x1, $0xf, %r3 + cdpeq $0x2, $0xe, %r4 cmn %r5, %r4 cmneq %r5, %r4 cmn %r5, $0x1 diff --git a/tests/project.conf b/tests/project.conf index b62bf48..dd72dd9 100644 --- a/tests/project.conf +++ b/tests/project.conf @@ -16,7 +16,7 @@ sources=arm.asm [arm.asm] asflags=-a arm -depends=../src/asm +depends=../src/arch/arm.so,../src/asm [armeb.o] type=object @@ -24,7 +24,7 @@ sources=armeb.asm [armeb.asm] asflags=-a armeb -depends=arm.asm,../src/asm +depends=../src/arch/armeb.so,arm.asm,../src/asm [armel.o] type=object @@ -32,7 +32,7 @@ sources=armel.asm [armel.asm] asflags=-a armel -depends=arm.asm,../src/asm +depends=../src/arch/armel.so,arm.asm,../src/asm [dalvik.o] type=object