From baa8076906b9741f00d6f7810e3f2b2abf87f41f Mon Sep 17 00:00:00 2001 From: Pierre Pronchery Date: Sat, 11 Jun 2011 23:33:55 +0000 Subject: [PATCH] Beginning to truly implement ARM support --- src/arch/arm.ins | 128 ++++++++++++++++++++++++++++++++++++++++++++++- src/arch/arm.reg | 53 ++------------------ test/arm.S | 5 ++ 3 files changed, 136 insertions(+), 50 deletions(-) diff --git a/src/arch/arm.ins b/src/arch/arm.ins index 97dffd1..6edef37 100644 --- a/src/arch/arm.ins +++ b/src/arch/arm.ins @@ -18,10 +18,134 @@ /* generic */ /* registers */ +/* conditions */ +#define eq 0x0 +#define ne 0x1 +#define cs 0x2 +#define cc 0x3 +#define mi 0x4 +#define pl 0x5 +#define vs 0x6 +#define vc 0x7 +#define hi 0x8 +#define ls 0x9 +#define ge 0xa +#define lt 0xb +#define gt 0xc +#define le 0xd +#define al 0xe + /* opcodes */ -#define OPNOP AO_IMMEDIATE(0, 32, 0) +#define OPNOP AO_IMMEDIATE(0, 32, 0) +#define OP_R AO_REGISTER(0, 32, 0) + +/* branch and exchange */ +#define OPBX(cond) (cond | 0x97ff9 << 4) + +/* data processing */ +#define OP_DATA2 AO_IMMEDIATE(0, 12, 0) /* instructions */ -/* FIXME verify */ +#if 1 /* FIXME really implement */ +{ "adc", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "add", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "and", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +/* b */ +{ "b", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "beq", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "bne", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "bcs", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "bcc", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "bmi", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "bpl", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "bvs", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "bvc", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "bhi", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "bls", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "bge", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "blt", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "bgt", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "bge", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "bal", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +/* bic */ +{ "bic", 0x00000000, OPNOP, OP_R, OP_R, OP_DATA2 }, +/* bl */ +{ "bl", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "bleq", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "blne", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "blcs", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "blcc", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "blmi", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "blpl", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "blvs", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "blvc", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "blhi", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "blls", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "blge", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "bllt", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "blgt", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "blge", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "blal", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +/* bx */ +{ "bx", OPBX(al), OPNOP, OP_R, AOT_NONE, AOT_NONE }, +{ "bxeq", OPBX(eq), OPNOP, OP_R, AOT_NONE, AOT_NONE }, +{ "bxne", OPBX(ne), OPNOP, OP_R, AOT_NONE, AOT_NONE }, +{ "bxcs", OPBX(cs), OPNOP, OP_R, AOT_NONE, AOT_NONE }, +{ "bxcc", OPBX(cc), OPNOP, OP_R, AOT_NONE, AOT_NONE }, +{ "bxmi", OPBX(mi), OPNOP, OP_R, AOT_NONE, AOT_NONE }, +{ "bxpl", OPBX(pl), OPNOP, OP_R, AOT_NONE, AOT_NONE }, +{ "bxvs", OPBX(vs), OPNOP, OP_R, AOT_NONE, AOT_NONE }, +{ "bxvc", OPBX(vc), OPNOP, OP_R, AOT_NONE, AOT_NONE }, +{ "bxhi", OPBX(hi), OPNOP, OP_R, AOT_NONE, AOT_NONE }, +{ "bxls", OPBX(ls), OPNOP, OP_R, AOT_NONE, AOT_NONE }, +{ "bxge", OPBX(ge), OPNOP, OP_R, AOT_NONE, AOT_NONE }, +{ "bxlt", OPBX(lt), OPNOP, OP_R, AOT_NONE, AOT_NONE }, +{ "bxgt", OPBX(gt), OPNOP, OP_R, AOT_NONE, AOT_NONE }, +{ "bxge", OPBX(ge), OPNOP, OP_R, AOT_NONE, AOT_NONE }, +{ "bxal", OPBX(al), OPNOP, OP_R, AOT_NONE, AOT_NONE }, +/* cdp */ +{ "cdp", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "cmn", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "cmp", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "eor", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "ldc", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "ldm", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "ldr", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "mla", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "mov", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "mrc", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "mrs", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE }, +/* msr */ +{ "msr", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE }, +{ "msreq", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE }, +{ "msrne", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE }, +{ "msrcs", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE }, +{ "msrcc", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE }, +{ "msrmi", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE }, +{ "msrpl", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE }, +{ "msrvs", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE }, +{ "msrvc", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE }, +{ "msrhi", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE }, +{ "msrls", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE }, +{ "msrge", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE }, +{ "msrlt", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE }, +{ "msrgt", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE }, +{ "msrle", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE }, +{ "msral", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE }, +{ "mul", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "mvn", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, { "nop", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "orr", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "rsb", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "rsc", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "sbc", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "stc", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "stm", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "str", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "sub", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "swi", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "swp", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "teq", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +{ "tst", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE }, +#endif diff --git a/src/arch/arm.reg b/src/arch/arm.reg index 232ea03..83a77d6 100644 --- a/src/arch/arm.reg +++ b/src/arch/arm.reg @@ -14,51 +14,8 @@ REG(r12, 32, 0x0c) REG(r13, 32, 0x0d) REG(r14, 32, 0x0e) REG(r15, 32, 0x0f) -REG(r16, 32, 0x10) -REG(r17, 32, 0x11) -REG(r18, 32, 0x12) -REG(r19, 32, 0x13) -REG(r20, 32, 0x14) -REG(r21, 32, 0x15) -REG(r22, 32, 0x16) -REG(r23, 32, 0x17) -REG(r24, 32, 0x18) -REG(r25, 32, 0x19) -REG(r26, 32, 0x1a) -REG(r27, 32, 0x1b) -REG(r28, 32, 0x1c) -REG(r29, 32, 0x1d) -REG(r30, 32, 0x1e) -REG(r31, 32, 0x1f) -REG(f0, 32, 0x31) -REG(f1, 32, 0x32) -REG(f2, 32, 0x33) -REG(f3, 32, 0x34) -REG(f4, 32, 0x35) -REG(f5, 32, 0x36) -REG(f6, 32, 0x37) -REG(f7, 32, 0x38) -REG(f8, 32, 0x39) -REG(f9, 32, 0x3a) -REG(f10, 32, 0x3b) -REG(f11, 32, 0x3c) -REG(f12, 32, 0x3d) -REG(f13, 32, 0x3e) -REG(f14, 32, 0x3f) -REG(f15, 32, 0x40) -REG(f16, 32, 0x41) -REG(f17, 32, 0x42) -REG(f18, 32, 0x43) -REG(f19, 32, 0x44) -REG(f20, 32, 0x45) -REG(f21, 32, 0x46) -REG(f22, 32, 0x47) -REG(f23, 32, 0x48) -REG(f24, 32, 0x49) -REG(f25, 32, 0x4a) -REG(f26, 32, 0x4b) -REG(f27, 32, 0x4c) -REG(f28, 32, 0x4d) -REG(f29, 32, 0x4e) -REG(f30, 32, 0x4f) -REG(f31, 32, 0x50) +REG(sp, 32, 0x0d) +REG(lr, 32, 0x0e) +REG(pc, 32, 0x0f) +REG(cpsr,32, 0x10) +REG(spsr,32, 0x11) diff --git a/test/arm.S b/test/arm.S index d1836f2..6cf3a05 100644 --- a/test/arm.S +++ b/test/arm.S @@ -1,2 +1,7 @@ .text + bx %r0 + bxeq %r0 + bic %r0, %r0, $0x1f + mrs %r0, %cpsr + msr %r0, %cpsr nop