diff --git a/src/arch/i386.ins b/src/arch/i386.ins
index be19c2f..1257d49 100644
--- a/src/arch/i386.ins
+++ b/src/arch/i386.ins
@@ -182,5 +182,23 @@
 { "and",	0x83,		OP1F, OP_RMW_D8+4,OP_S8,     AOT_NONE	},
 { "and",	0x83,		OP1F, OP_RMW_DW+4,OP_S8,     AOT_NONE	},
 { "and",	0x83,		OP1F, OP_RMW_RW+4,OP_S8,     AOT_NONE	},
+/* ARPL */
+/* FIXME implement */
+/* BOUND */
+/* FIXME implement */
+/* BSF		0x0fbc		2     rW          r/mW			*/
+#if 1 /* FIXME doesn't work at the moment */
+{ "bsf",	0x0fbc,		OP2F, OP_RMW_RW_R,OP_RMW_D0_R,AOT_NONE	},
+{ "bsf",	0x0fbc,		OP2F, OP_RMW_RW_R,OP_RMW_D8_R,AOT_NONE	},
+{ "bsf",	0x0fbc,		OP2F, OP_RMW_RW_R,OP_RMW_DW_R,AOT_NONE	},
+{ "bsf",	0x0fbc,		OP2F, OP_RMW_RW_R,OP_RMW_RW_R,AOT_NONE	},
+#endif
+/* BSR		0x0fbd		2     rW          r/mW			*/
+#if 1 /* FIXME doesn't work at the moment */
+{ "bsr",	0x0fbd,		OP2F, OP_RMW_RW_R,OP_RMW_D0_R,AOT_NONE	},
+{ "bsr",	0x0fbd,		OP2F, OP_RMW_RW_R,OP_RMW_D8_R,AOT_NONE	},
+{ "bsr",	0x0fbd,		OP2F, OP_RMW_RW_R,OP_RMW_DW_R,AOT_NONE	},
+{ "bsr",	0x0fbd,		OP2F, OP_RMW_RW_R,OP_RMW_RW_R,AOT_NONE	},
+#endif
 /* NOP									*/
 { "nop",	0x90,		OP1F, AOT_NONE,   AOT_NONE,  AOT_NONE	},
diff --git a/test/i386.S b/test/i386.S
index f7b4a3f..69803d2 100644
--- a/test/i386.S
+++ b/test/i386.S
@@ -46,5 +46,13 @@
 	add	%ecx, $0x45464748		/* 81 c1 45 46 47 48	*/
 	/* AND */
 	and	%ecx, $0x45464748		/* 81 e1 45 46 47 48	*/
+	/* BSF */
+#if 1 /* FIXME doesn't work at the moment */
+	bsf	%eax, [%eax]			/* 0f bc		*/
+#endif
+	/* BSR */
+#if 1 /* FIXME doesn't work at the moment */
+	bsr	%eax, [%eax]			/* 0f bd		*/
+#endif
 	/* NOP */
 	nop