The Yasep processor is really little-endian
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953ecb2013
commit
ce3a785edd
@ -17,6 +17,7 @@
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#include <stddef.h>
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#include "Asm.h"
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#define ARCH_yasep32
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/* yasep */
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@ -113,7 +114,7 @@ static int _encode_16(ArchPlugin * plugin, ArchInstruction * instruction,
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return -1;
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u16 |= ar->id << 8;
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}
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u16 = _htob16(u16);
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u16 = _htol16(u16);
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if(helper->write(helper->arch, &u16, sizeof(u16)) != sizeof(u16))
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return -1;
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return 0;
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@ -125,7 +126,7 @@ static int _encode_32(ArchPlugin * plugin, ArchInstruction * instruction,
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ArchPluginHelper * helper = plugin->helper;
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uint32_t opcode = instruction->opcode;
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opcode = _htob32(opcode);
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opcode = _htol32(opcode);
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if(helper->write(helper->arch, &opcode, sizeof(opcode))
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!= sizeof(opcode))
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return -1;
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@ -144,7 +145,7 @@ static int _yasep_decode(ArchPlugin * plugin, ArchInstructionCall * call)
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if(helper->read(helper->arch, &u16, sizeof(u16)) != sizeof(u16))
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return -1;
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u16 = _htob16(u16);
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u16 = _htol16(u16);
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opcode = u16 & 0x00ff;
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if((ai = helper->get_instruction_by_opcode(helper->arch, 16, opcode))
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== NULL)
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@ -15,33 +15,53 @@
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/* platform-specific */
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#if !defined(W)
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# if defined(ARCH_yasep16)
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# define W 16
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# else
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# define W 32
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# endif
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#endif
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/* generic */
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/* opcode */
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#define OPI(opcode) ((opcode << 2) | 0x2)
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#define OPIR(opcode) ((opcode << 2) | 0x2)
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#define OPR(opcode) (opcode << 2)
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#define OPRI(opcode) ((opcode << 2) | 0x2)
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#define OPRR(opcode) (opcode << 2)
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#define OPIRL(opcode) ((opcode << 2) | 0x1)
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#define OPRRL(opcode) ((opcode << 2) | 0x3)
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#define OPLIR(opcode) ((opcode << 2) | 0x1)
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#define OPLIRR(opcode) ((opcode << 2) | 0x3 | (0x1 << 17))
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#define OPLRI(opcode) ((opcode << 2) | 0x1)
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#define OPLRIR(opcode) ((opcode << 2) | 0x1)
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#define OPLRRR(opcode) ((opcode << 2) | 0x3)
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/* flags */
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#define OPIF (16 << AOD_SIZE)
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#define OPIRF (16 << AOD_SIZE)
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#define OPRF (16 << AOD_SIZE)
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#define OPRIF (16 << AOD_SIZE)
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#define OPRRF (16 << AOD_SIZE)
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#define OPIRLF (32 << AOD_SIZE)
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#define OPRRLF (32 << AOD_SIZE)
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#define OPLIRF (32 << AOD_SIZE)
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#define OPLIRRF (32 << AOD_SIZE)
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#define OPLRIF (32 << AOD_SIZE)
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#define OPLRIRF (32 << AOD_SIZE)
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#define OPLRRRF (32 << AOD_SIZE)
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/* operands */
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#define OP_DST3 AO_REGISTER(0, 16, 0)
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#define OP_DST3 AO_REGISTER(0, W, 0)
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#define OP_IMM4 AO_IMMEDIATE(0, 4, 0)
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#define OP_IMM16 AO_IMMEDIATE(0, 16, 0)
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#define OP_SI4 AO_REGISTER(0, 16, 0)
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#define OP_SND AO_REGISTER(0, 16, 0)
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#define OP_IMM16 AO_IMMEDIATE(0, W, 0)
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#define OP_SI4 AO_REGISTER(0, W, 0)
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#define OP_SND AO_REGISTER(0, W, 0)
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/* instructions */
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{ "add", OPIR(0x03), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "add", OPRR(0x03), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "add", OPIRL(0x03),OPIRLF, AO_2(OP_SI4, OP_IMM16) },
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{ "add", OPRRL(0x03),OPRRLF, AO_3(OP_SND, OP_SI4, OP_DST3) },
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{ "add", OPLIRR(0x03),OPLIRRF, AO_3(OP_IMM16, OP_SND, OP_DST3) },
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{ "add", OPLRIR(0x03),OPLRIRF, AO_3(OP_SI4, OP_IMM16, OP_SND) },
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{ "add", OPLRRR(0x03),OPLRRRF, AO_3(OP_SND, OP_SI4, OP_DST3) },
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{ "and", OPIR(0x02), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "and", OPRR(0x02), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "and", OPIRL(0x02),OPIRLF, AO_2(OP_SI4, OP_IMM16) },
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{ "and", OPRRL(0x02),OPRRLF, AO_3(OP_SND, OP_SI4, OP_DST3) },
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{ "andn", OPIR(0x0a), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "andn", OPRR(0x0a), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "cmps", OPIR(0x1b), OPIRF, AO_2(OP_IMM4, OP_SND) },
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@ -50,24 +70,34 @@
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{ "cmpu", OPRR(0x13), OPRRF, AO_2(OP_SI4, OP_SND) },
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#if 0 /* XXX aliases */
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{ "esb", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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# if defined(ARCH_yasep32)
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{ "esh", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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# endif
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{ "ezb", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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# if defined(ARCH_yasep32)
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{ "ezh", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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# endif
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#endif
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{ "get", OPIR(0x05), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "get", OPRR(0x05), OPRRF, AO_2(OP_SI4, OP_SND) },
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#if 0 /* XXX aliases */
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{ "ib", OPIR(0x00), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "ib", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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# if defined(ARCH_yasep32)
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{ "ih", OPIR(0x00), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "ih", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "ihh", OPIR(0x00), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "ihh", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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# endif
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#endif
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{ "lsb", OPRR(0x18), OPRRF, AO_2(OP_SI4, OP_SND) },
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#if defined(ARCH_yasep32)
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{ "lsh", OPRR(0x38), OPRRF, AO_2(OP_SI4, OP_SND) },
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#endif
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{ "lzb", OPRR(0x10), OPRRF, AO_2(OP_SI4, OP_SND) },
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#if defined(ARCH_yasep32)
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{ "lzh", OPRR(0x30), OPRRF, AO_2(OP_SI4, OP_SND) },
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#endif
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{ "mov", OPIR(0x00), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "mov", OPRR(0x00), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "mul8h", OPIR(0x0c), OPIRF, AO_2(OP_IMM4, OP_SND) },
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@ -99,10 +129,12 @@
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{ "sar", OPRR(0x09), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "sb", OPIR(0x08), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "sb", OPRR(0x08), OPRRF, AO_2(OP_SI4, OP_SND) },
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#if defined(ARCH_yasep32)
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{ "sh", OPIR(0x20), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "sh", OPRR(0x20), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "shh", OPIR(0x28), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "shh", OPRR(0x28), OPRRF, AO_2(OP_SI4, OP_SND) },
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#endif
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{ "shl", OPIR(0x11), OPIRF, AO_2(OP_IMM4, OP_SND) },
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{ "shl", OPRR(0x11), OPRRF, AO_2(OP_SI4, OP_SND) },
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{ "shr", OPIR(0x01), OPIRF, AO_2(OP_IMM4, OP_SND) },
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@ -1,32 +1,40 @@
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REG(npc, 16, 0x00)
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REG(r1, 16, 0x01)
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REG(r2, 16, 0x02)
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REG(r3, 16, 0x03)
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REG(r4, 16, 0x04)
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REG(r5, 16, 0x05)
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REG(d5, 16, 0x06)
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REG(a5, 16, 0x07)
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REG(d4, 16, 0x08)
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REG(a4, 16, 0x09)
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REG(d3, 16, 0x0a)
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REG(a3, 16, 0x0b)
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REG(d2, 16, 0x0c)
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REG(a2, 16, 0x0d)
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REG(d1, 16, 0x0e)
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REG(a1, 16, 0x0f)
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REG(r0, 16, 0x00)
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REG(r1, 16, 0x01)
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REG(r2, 16, 0x02)
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REG(r3, 16, 0x03)
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REG(r4, 16, 0x04)
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REG(r5, 16, 0x05)
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REG(r6, 16, 0x06)
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REG(r7, 16, 0x07)
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REG(r8, 16, 0x08)
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REG(r9, 16, 0x09)
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REG(r10, 16, 0x0a)
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REG(r11, 16, 0x0b)
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REG(r12, 16, 0x0c)
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REG(r13, 16, 0x0d)
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REG(r14, 16, 0x0e)
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REG(r15, 16, 0x0f)
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/* platform-specific */
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#if !defined(W)
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# if defined(ARCH_yasep16)
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# define W 16
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# else
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# define W 32
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# endif
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#endif
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REG(npc, W, 0x00)
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REG(r1, W, 0x01)
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REG(r2, W, 0x02)
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REG(r3, W, 0x03)
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REG(r4, W, 0x04)
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REG(r5, W, 0x05)
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REG(d5, W, 0x06)
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REG(a5, W, 0x07)
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REG(d4, W, 0x08)
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REG(a4, W, 0x09)
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REG(d3, W, 0x0a)
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REG(a3, W, 0x0b)
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REG(d2, W, 0x0c)
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REG(a2, W, 0x0d)
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REG(d1, W, 0x0e)
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REG(a1, W, 0x0f)
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REG(r0, W, 0x00)
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REG(r1, W, 0x01)
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REG(r2, W, 0x02)
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REG(r3, W, 0x03)
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REG(r4, W, 0x04)
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REG(r5, W, 0x05)
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REG(r6, W, 0x06)
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REG(r7, W, 0x07)
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REG(r8, W, 0x08)
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REG(r9, W, 0x09)
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REG(r10, W, 0x0a)
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REG(r11, W, 0x0b)
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REG(r12, W, 0x0c)
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REG(r13, W, 0x0d)
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REG(r14, W, 0x0e)
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REG(r15, W, 0x0f)
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