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The "adc" instruction doesn't care for the signedness

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This commit is contained in:
Pierre Pronchery 2011-04-17 05:36:12 +00:00
parent 59e1799a37
commit d1d16311a7
4 changed files with 30 additions and 17 deletions
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4
src/arch.c
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@ -282,6 +282,10 @@ static int _call_operands_immediate(ArchOperandDefinition definition,
value >>= size; value >>= size;
if(value > 0) if(value > 0)
return -1; return -1;
/* check if it is signed */
if(operand->value.immediate.negative
&& !(AO_GET_FLAGS(definition) & AOF_SIGNED))
return -1;
return 0; return 0;
} }

13
src/arch/i386.c
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@ -175,19 +175,20 @@ static int _write_dregister(ArchPlugin * plugin, uint32_t * i,
static int _write_immediate(ArchPlugin * plugin, static int _write_immediate(ArchPlugin * plugin,
ArchOperandDefinition definition, ArchOperand * operand) ArchOperandDefinition definition, ArchOperand * operand)
{ {
uint64_t value = operand->value.immediate.value;
if(AO_GET_FLAGS(definition) & AOF_SIGNED)
value = -value;
switch(AO_GET_SIZE(definition) >> 3) switch(AO_GET_SIZE(definition) >> 3)
{ {
case 0: case 0:
return 0; return 0;
case sizeof(uint8_t): case sizeof(uint8_t):
return _write_immediate8(plugin, return _write_immediate8(plugin, value);
operand->value.immediate.value);
case sizeof(uint16_t): case sizeof(uint16_t):
return _write_immediate16(plugin, return _write_immediate16(plugin, value);
operand->value.immediate.value);
case sizeof(uint32_t): case sizeof(uint32_t):
return _write_immediate32(plugin, return _write_immediate32(plugin, value);
operand->value.immediate.value);
default: default:
return -1; return -1;
} }

29
src/arch/i386.ins
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@ -36,6 +36,8 @@
#define OP_RMW_RW AO_REGISTER(AOF_I386_MODRM, W, 0) /* 0xc0 */ #define OP_RMW_RW AO_REGISTER(AOF_I386_MODRM, W, 0) /* 0xc0 */
/* immediate values */ /* immediate values */
#define OP_S8 AO_IMMEDIATE(AOF_SIGNED, 0, 8)
#define OP_SW AO_IMMEDIATE(AOF_SIGNED, 0, W)
#define OP_U8 AO_IMMEDIATE(0, 0, 8) #define OP_U8 AO_IMMEDIATE(0, 0, 8)
#define OP_UW AO_IMMEDIATE(0, 0, W) #define OP_UW AO_IMMEDIATE(0, 0, W)
@ -60,19 +62,24 @@
{ "adc", 0x12, OP1F, OP_RM8_R8_R,OP_RM8_R8_R,AOT_NONE }, { "adc", 0x12, OP1F, OP_RM8_R8_R,OP_RM8_R8_R,AOT_NONE },
#endif #endif
/* ADC 0x14 ib 1 al imm8 */ /* ADC 0x14 ib 1 al imm8 */
{ "adc", 0x14, OP1F, OP_al, OP_U8, AOT_NONE }, { "adc", 0x14, OP1F, OP_al, OP_S8, AOT_NONE },
/* ADC 0x15 iW 1 AX immW */ /* ADC 0x15 iW 1 AX immW */
{ "adc", 0x15, OP1F, OP_AX, OP_UW, AOT_NONE }, { "adc", 0x15, OP1F, OP_AX, OP_SW, AOT_NONE },
/* ADC 0x80 /2 ib 1 r/m8 imm8 */ /* ADC 0x80 /2 ib 1 r/m8 imm8 */
{ "adc", 0x80, OP1F, OP_RM8_D0+2,OP_U8, AOT_NONE }, { "adc", 0x80, OP1F, OP_RM8_D0+2,OP_S8, AOT_NONE },
{ "adc", 0x80, OP1F, OP_RM8_D8+2,OP_U8, AOT_NONE }, { "adc", 0x80, OP1F, OP_RM8_D8+2,OP_S8, AOT_NONE },
{ "adc", 0x80, OP1F, OP_RM8_DW+2,OP_U8, AOT_NONE }, { "adc", 0x80, OP1F, OP_RM8_DW+2,OP_S8, AOT_NONE },
{ "adc", 0x80, OP1F, OP_RM8_R8+2,OP_U8, AOT_NONE }, { "adc", 0x80, OP1F, OP_RM8_R8+2,OP_S8, AOT_NONE },
/* ADC 0x81 /2 iW 1 r/m8 imm8 */ /* ADC 0x81 /2 iW 1 r/m8 imm8 */
{ "adc", 0x81, OP1F, OP_RMW_D0+2,OP_UW, AOT_NONE }, { "adc", 0x81, OP1F, OP_RMW_D0+2,OP_SW, AOT_NONE },
{ "adc", 0x81, OP1F, OP_RMW_D8+2,OP_UW, AOT_NONE }, { "adc", 0x81, OP1F, OP_RMW_D8+2,OP_SW, AOT_NONE },
{ "adc", 0x81, OP1F, OP_RMW_DW+2,OP_UW, AOT_NONE }, { "adc", 0x81, OP1F, OP_RMW_DW+2,OP_SW, AOT_NONE },
{ "adc", 0x81, OP1F, OP_RMW_RW+2,OP_UW, AOT_NONE }, { "adc", 0x81, OP1F, OP_RMW_RW+2,OP_SW, AOT_NONE },
/* ADC 0x83 /2 i8 1 r/m8 imm8 */
{ "adc", 0x83, OP1F, OP_RMW_D0+2,OP_S8, AOT_NONE },
{ "adc", 0x83, OP1F, OP_RMW_D8+2,OP_S8, AOT_NONE },
{ "adc", 0x83, OP1F, OP_RMW_DW+2,OP_S8, AOT_NONE },
{ "adc", 0x83, OP1F, OP_RMW_RW+2,OP_S8, AOT_NONE },
/* ADD 0x04 ib 1 al imm8 */ /* ADD 0x04 ib 1 al imm8 */
{ "add", 0x04, OP1F, OP_al, OP_U8, AOT_NONE }, { "add", 0x04, OP1F, OP_al, OP_U8, AOT_NONE },
/* ADD 0x05 iW 1 AX immW */ /* ADD 0x05 iW 1 AX immW */
@ -82,7 +89,7 @@
{ "add", 0x80, OP1F, OP_RM8_D8+0,OP_U8, AOT_NONE }, { "add", 0x80, OP1F, OP_RM8_D8+0,OP_U8, AOT_NONE },
{ "add", 0x80, OP1F, OP_RM8_DW+0,OP_U8, AOT_NONE }, { "add", 0x80, OP1F, OP_RM8_DW+0,OP_U8, AOT_NONE },
{ "add", 0x80, OP1F, OP_RM8_R8+0,OP_U8, AOT_NONE }, { "add", 0x80, OP1F, OP_RM8_R8+0,OP_U8, AOT_NONE },
/* ADC 0x81 /0 iW 1 r/m8 imm8 */ /* ADD 0x81 /0 iW 1 r/m8 imm8 */
{ "add", 0x81, OP1F, OP_RMW_D0+0,OP_UW, AOT_NONE }, { "add", 0x81, OP1F, OP_RMW_D0+0,OP_UW, AOT_NONE },
{ "add", 0x81, OP1F, OP_RMW_D8+0,OP_UW, AOT_NONE }, { "add", 0x81, OP1F, OP_RMW_D8+0,OP_UW, AOT_NONE },
{ "add", 0x81, OP1F, OP_RMW_DW+0,OP_UW, AOT_NONE }, { "add", 0x81, OP1F, OP_RMW_DW+0,OP_UW, AOT_NONE },

1
test/i386.S
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@ -26,6 +26,7 @@
/* 81 93 19 18 17 16 4b */ /* 81 93 19 18 17 16 4b */
/* 4a 49 48 */ /* 4a 49 48 */
adc %ecx, $0x45464748 /* 81 d1 45 46 47 48 */ adc %ecx, $0x45464748 /* 81 d1 45 46 47 48 */
adc [%eax], -$0x02 /* 83 10 fe */
/* ADD */ /* ADD */
add %al, $0x40 /* 04 40 */ add %al, $0x40 /* 04 40 */
add %eax, $0x41424344 /* 05 44 43 42 41 */ add %eax, $0x41424344 /* 05 44 43 42 41 */