DeforaOS/Asm
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Supporting more operands (not complete)

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This commit is contained in:
Pierre Pronchery 2011-09-28 03:05:25 +00:00
parent 9ad09b3bf1
commit f534d59a0a
1 changed files with 13 additions and 13 deletions
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26
src/arch/i386.ins
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@ -147,9 +147,9 @@
{ "aas", 0x3f, OP1F, AO_0() }, { "aas", 0x3f, OP1F, AO_0() },
#endif #endif
/* ADC 0x14 ib 1 al imm8 */ /* ADC 0x14 ib 1 al imm8 */
{ "adc", 0x14, OP1F, OP_al, OP_S8, AOT_NONE }, { "adc", 0x14, OP1F, AO_2(OP_al, OP_S8) },
/* ADC 0x15 iW 1 AX immW */ /* ADC 0x15 iW 1 AX immW */
{ "adc", 0x15, OP1F, OP_AX, OP_SW, AOT_NONE }, { "adc", 0x15, OP1F, AO_2(OP_AX, OP_SW) },
/* ADC 0x10 /r 1 r/m8 r8 */ /* ADC 0x10 /r 1 r/m8 r8 */
{ "adc", 0x10, OP1F, AO_2(OP_RM8_D0, OP_R8_R) }, { "adc", 0x10, OP1F, AO_2(OP_RM8_D0, OP_R8_R) },
{ "adc", 0x10, OP1F, AO_2(OP_RM8_D8, OP_R8_R) }, { "adc", 0x10, OP1F, AO_2(OP_RM8_D8, OP_R8_R) },
@ -190,9 +190,9 @@
{ "adcb", 0x83, OP1F, AO_2(OP_RMW_DW+2, OP_S8) }, { "adcb", 0x83, OP1F, AO_2(OP_RMW_DW+2, OP_S8) },
{ "adc", 0x83, OP1F, AO_2(OP_RMW_RW+2, OP_S8) }, { "adc", 0x83, OP1F, AO_2(OP_RMW_RW+2, OP_S8) },
/* ADD 0x04 ib 1 al imm8 */ /* ADD 0x04 ib 1 al imm8 */
{ "add", 0x04, OP1F, OP_al, OP_S8, AOT_NONE }, { "add", 0x04, OP1F, AO_2(OP_al, OP_S8) },
/* ADD 0x05 iW 1 AX immW */ /* ADD 0x05 iW 1 AX immW */
{ "add", 0x05, OP1F, OP_AX, OP_SW, AOT_NONE }, { "add", 0x05, OP1F, AO_2(OP_AX, OP_SW) },
/* ADD 0x00 /r 1 r/m8 r8 */ /* ADD 0x00 /r 1 r/m8 r8 */
{ "add", 0x00, OP1F, AO_2(OP_RM8_D0, OP_R8_R) }, { "add", 0x00, OP1F, AO_2(OP_RM8_D0, OP_R8_R) },
{ "add", 0x00, OP1F, AO_2(OP_RM8_D8, OP_R8_R) }, { "add", 0x00, OP1F, AO_2(OP_RM8_D8, OP_R8_R) },
@ -693,13 +693,13 @@
/* IMUL */ /* IMUL */
/* FIXME implement */ /* FIXME implement */
/* IN 0xe4 1 al imm8 */ /* IN 0xe4 1 al imm8 */
{ "in", 0xe4, OP1F, OP_al, OP_S8, AOT_NONE }, { "in", 0xe4, OP1F, AO_2(OP_al, OP_S8) },
/* IN 0xe5 1 AX imm8 */ /* IN 0xe5 1 AX imm8 */
{ "in", 0xe5, OP1F, OP_AX, OP_S8, AOT_NONE }, { "in", 0xe5, OP1F, AO_2(OP_AX, OP_S8) },
/* IN 0xec 1 al dx */ /* IN 0xec 1 al dx */
{ "in", 0xec, OP1F, OP_al, OP_dx, AOT_NONE }, { "in", 0xec, OP1F, AO_2(OP_al, OP_dx) },
/* IN 0xed 1 AX dx */ /* IN 0xed 1 AX dx */
{ "in", 0xed, OP1F, OP_AX, OP_dx, AOT_NONE }, { "in", 0xed, OP1F, AO_2(OP_AX, OP_dx) },
/* INC 0x40 +rd 1 */ /* INC 0x40 +rd 1 */
{ "inc", 0x40, OP1F, AO_1(OP_AX) }, { "inc", 0x40, OP1F, AO_1(OP_AX) },
{ "inc", 0x41, OP1F, AO_1(OP_CX) }, { "inc", 0x41, OP1F, AO_1(OP_CX) },
@ -931,13 +931,13 @@
/* MOV 0xa0 1 al moffs8 */ /* MOV 0xa0 1 al moffs8 */
{ "mov", 0xa0, OP1F, OP_al, OP_SW, AOT_NONE }, { "mov", 0xa0, OP1F, OP_al, OP_SW, AOT_NONE },
/* MOV 0xa1 1 AX moffs16 */ /* MOV 0xa1 1 AX moffs16 */
{ "mov", 0xa1, OP1F, OP_AX, OP_SW, AOT_NONE }, { "mov", 0xa1, OP1F, AO_2(OP_AX, OP_SW) },
/* MOV 0xa2 1 moffs8 al */ /* MOV 0xa2 1 moffs8 al */
{ "mov", 0xa2, OP1F, OP_SW, OP_al, AOT_NONE }, { "mov", 0xa2, OP1F, OP_SW, OP_al, AOT_NONE },
/* MOV 0xa3 1 moffsW AX */ /* MOV 0xa3 1 moffsW AX */
{ "mov", 0xa3, OP1F, OP_SW, OP_AX, AOT_NONE }, { "mov", 0xa3, OP1F, OP_SW, OP_AX, AOT_NONE },
/* MOV 0xb0 +rb 1 r8 imm8 */ /* MOV 0xb0 +rb 1 r8 imm8 */
{ "mov", 0xb0, OP1F, OP_al, OP_S8, AOT_NONE }, { "mov", 0xb0, OP1F, AO_2(OP_al, OP_S8) },
{ "mov", 0xb1, OP1F, OP_cl, OP_S8, AOT_NONE }, { "mov", 0xb1, OP1F, OP_cl, OP_S8, AOT_NONE },
{ "mov", 0xb2, OP1F, OP_dl, OP_S8, AOT_NONE }, { "mov", 0xb2, OP1F, OP_dl, OP_S8, AOT_NONE },
{ "mov", 0xb3, OP1F, OP_bl, OP_S8, AOT_NONE }, { "mov", 0xb3, OP1F, OP_bl, OP_S8, AOT_NONE },
@ -946,7 +946,7 @@
{ "mov", 0xb6, OP1F, OP_dh, OP_S8, AOT_NONE }, { "mov", 0xb6, OP1F, OP_dh, OP_S8, AOT_NONE },
{ "mov", 0xb7, OP1F, OP_bh, OP_S8, AOT_NONE }, { "mov", 0xb7, OP1F, OP_bh, OP_S8, AOT_NONE },
/* MOV 0xb8 +rw 1 rW immW */ /* MOV 0xb8 +rw 1 rW immW */
{ "mov", 0xb8, OP1F, OP_AX, OP_SW, AOT_NONE }, { "mov", 0xb8, OP1F, AO_2(OP_AX, OP_SW) },
{ "mov", 0xb9, OP1F, OP_CX, OP_SW, AOT_NONE }, { "mov", 0xb9, OP1F, OP_CX, OP_SW, AOT_NONE },
{ "mov", 0xba, OP1F, OP_DX, OP_SW, AOT_NONE }, { "mov", 0xba, OP1F, OP_DX, OP_SW, AOT_NONE },
{ "mov", 0xbb, OP1F, OP_BX, OP_SW, AOT_NONE }, { "mov", 0xbb, OP1F, OP_BX, OP_SW, AOT_NONE },
@ -1377,9 +1377,9 @@
{ "subb", 0x83, OP1F, AO_2(OP_RMW_DW+5, OP_S8) }, { "subb", 0x83, OP1F, AO_2(OP_RMW_DW+5, OP_S8) },
{ "sub", 0x83, OP1F, AO_2(OP_RMW_RW+5, OP_S8) }, { "sub", 0x83, OP1F, AO_2(OP_RMW_RW+5, OP_S8) },
/* TEST 0xa8 ib 1 al imm8 */ /* TEST 0xa8 ib 1 al imm8 */
{ "test", 0xa8, OP1F, OP_al, OP_S8, AOT_NONE }, { "test", 0xa8, OP1F, AO_2(OP_al, OP_S8) },
/* TEST 0xa9 iW 1 AX immW */ /* TEST 0xa9 iW 1 AX immW */
{ "test", 0xa9, OP1F, OP_AX, OP_SW, AOT_NONE }, { "test", 0xa9, OP1F, AO_2(OP_AX, OP_SW) },
/* TEST 0xf6 /0 ib 1 r/m8 imm8 */ /* TEST 0xf6 /0 ib 1 r/m8 imm8 */
{ "testb", 0xf6, OP1F, AO_2(OP_RM8_D0+0, OP_S8) }, { "testb", 0xf6, OP1F, AO_2(OP_RM8_D0+0, OP_S8) },
{ "testb", 0xf6, OP1F, AO_2(OP_RM8_D8+0, OP_S8) }, { "testb", 0xf6, OP1F, AO_2(OP_RM8_D8+0, OP_S8) },