/* $Id$ */
/* Copyright (c) 2011 Pierre Pronchery <khorben@defora.org> */
/* This file is part of DeforaOS Devel asm */
/* This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, version 3 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>. */



/* generic */
/* opcode */
#define OPIR(opcode)	((opcode << 2) | 0x2)
#define OPRR(opcode)	(opcode << 2)
#define OPIRL(opcode)	((opcode << 2) | 0x1)
#define OPRRL(opcode)	((opcode << 2) | 0x3)
/* flags */
#define OPIRF		(16 << AOD_SIZE)
#define OPRRF		(16 << AOD_SIZE)
#define OPIRLF		(32 << AOD_SIZE)
#define OPRRLF		(32 << AOD_SIZE)
/* operands */
#define OP_DST3		AO_REGISTER(0, 16, 0)
#define OP_IMM4		AO_IMMEDIATE(0, 4, 0)
#define OP_IMM16	AO_IMMEDIATE(0, 16, 0)
#define OP_SI4		AO_REGISTER(0, 16, 0)
#define OP_SND		AO_REGISTER(0, 16, 0)

/* instructions */
{ "add",	OPIR(0x03), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "add",	OPRR(0x03), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "add",	OPIRL(0x03),OPIRLF, AO_2(OP_SI4, OP_IMM16)		},
{ "add",	OPRRL(0x03),OPRRLF, AO_3(OP_SND, OP_SI4, OP_DST3)	},
{ "and",	OPIR(0x02), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "and",	OPRR(0x02), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "and",	OPIRL(0x02),OPIRLF, AO_2(OP_SI4, OP_IMM16)		},
{ "and",	OPRRL(0x02),OPRRLF, AO_3(OP_SND, OP_SI4, OP_DST3)	},
{ "andn",	OPIR(0x0a), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "andn",	OPRR(0x0a), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "cmps",	OPIR(0x1b), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "cmps",	OPRR(0x1b), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "cmpu",	OPIR(0x13), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "cmpu",	OPRR(0x13), OPRRF,  AO_2(OP_SI4, OP_SND)		},
#if 0 /* XXX aliases */
{ "esb",	OPRR(0x00), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "esh",	OPRR(0x00), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "ezb",	OPRR(0x00), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "ezh",	OPRR(0x00), OPRRF,  AO_2(OP_SI4, OP_SND)		},
#endif
{ "get",	OPIR(0x05), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "get",	OPRR(0x05), OPRRF,  AO_2(OP_SI4, OP_SND)		},
#if 0 /* XXX aliases */
{ "ib",		OPIR(0x00), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "ib",		OPRR(0x00), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "ih",		OPIR(0x00), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "ih",		OPRR(0x00), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "ihh",	OPIR(0x00), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "ihh",	OPRR(0x00), OPRRF,  AO_2(OP_SI4, OP_SND)		},
#endif
{ "lsb",	OPRR(0x18), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "lsh",	OPRR(0x38), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "lzb",	OPRR(0x10), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "lzh",	OPRR(0x30), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "mov",	OPIR(0x00), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "mov",	OPRR(0x00), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "mul8h",	OPIR(0x0c), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "mul8h",	OPRR(0x0c), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "mul8l",	OPIR(0x04), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "mul8l",	OPRR(0x04), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "muli",	OPIR(0x14), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "muli",	OPRR(0x14), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "nand",	OPIR(0x12), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "nand",	OPRR(0x12), OPRRF,  AO_2(OP_SI4, OP_SND)		},
#if 0 /* XXX alias */
{ "neg",	OPRR(0x00), OPRRF,  AO_2(OP_SI4, OP_SND)		},
#endif
{ "nor",	OPIR(0x2a), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "nor",	OPRR(0x2a), OPRRF,  AO_2(OP_SI4, OP_SND)		},
#if 0 /* XXX alias */
{ "not",	OPRR(0x00), OPRRF,  AO_2(OP_SI4, OP_SND)		},
#endif
{ "or",		OPIR(0x1a), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "or",		OPRR(0x1a), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "orn",	OPIR(0x22), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "orn",	OPRR(0x22), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "put",	OPRR(0x0d), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "rol",	OPIR(0x21), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "rol",	OPRR(0x21), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "ror",	OPIR(0x19), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "ror",	OPRR(0x19), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "sar",	OPIR(0x09), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "sar",	OPRR(0x09), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "sb",		OPIR(0x08), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "sb",		OPRR(0x08), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "sh",		OPIR(0x20), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "sh",		OPRR(0x20), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "shh",	OPIR(0x28), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "shh",	OPRR(0x28), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "shl",	OPIR(0x11), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "shl",	OPRR(0x11), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "shr",	OPIR(0x01), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "shr",	OPRR(0x01), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "smax",	OPIR(0x3b), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "smax",	OPRR(0x3b), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "smin",	OPIR(0x33), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "smin",	OPRR(0x33), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "sub",	OPIR(0x0b), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "sub",	OPRR(0x0b), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "umax",	OPIR(0x2b), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "umax",	OPRR(0x2b), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "umin",	OPIR(0x23), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "umin",	OPRR(0x23), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "xor",	OPIR(0x32), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "xor",	OPRR(0x32), OPRRF,  AO_2(OP_SI4, OP_SND)		},
{ "xorn",	OPIR(0x3a), OPIRF,  AO_2(OP_IMM4, OP_SND)		},
{ "xorn",	OPRR(0x3a), OPRRF,  AO_2(OP_SI4, OP_SND)		},
