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Asm/src/arch/i386.ins

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/* $Id$ */
/* Copyright (c) 2011 Pierre Pronchery <khorben@defora.org> */
/* This file is part of DeforaOS Devel asm */
/* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* platform-specific */
#if defined(ARCH_i386_real) /* i386 in real mode */
# define W 16
# define REG_AX_id REG_ax_id
# define REG_CX_id REG_cx_id
# define REG_DX_id REG_dx_id
# define REG_BX_id REG_bx_id
# define REG_SP_id REG_sp_id
# define REG_BP_id REG_bp_id
# define REG_SI_id REG_si_id
# define REG_DI_id REG_di_id
#else /* i386 and compatible in 32-bit protected mode */
# define W 32
# define REG_AX_id REG_eax_id
# define REG_CX_id REG_ecx_id
# define REG_DX_id REG_edx_id
# define REG_BX_id REG_ebx_id
# define REG_SP_id REG_esp_id
# define REG_BP_id REG_ebp_id
# define REG_SI_id REG_esi_id
# define REG_DI_id REG_edi_id
#endif
/* helpers */
/* opcodes */
#define OP1F (8 << AOD_SIZE)
#define OP2F (16 << AOD_SIZE)
#define OP3F (24 << AOD_SIZE)
/* operands */
/* registers */
#define OP_R8 AO_REGISTER(0, 8, 0)
#define OP_RW AO_REGISTER(0, W, 0)
#define OP_al AO_REGISTER(AOF_IMPLICIT, REG_al_size, REG_al_id)
#define OP_AX AO_REGISTER(AOF_IMPLICIT, W, REG_AX_id)
#define OP_CX AO_REGISTER(AOF_IMPLICIT, W, REG_CX_id)
#define OP_DX AO_REGISTER(AOF_IMPLICIT, W, REG_DX_id)
#define OP_BX AO_REGISTER(AOF_IMPLICIT, W, REG_BX_id)
#define OP_SP AO_REGISTER(AOF_IMPLICIT, W, REG_SP_id)
#define OP_BP AO_REGISTER(AOF_IMPLICIT, W, REG_BP_id)
#define OP_SI AO_REGISTER(AOF_IMPLICIT, W, REG_SI_id)
#define OP_DI AO_REGISTER(AOF_IMPLICIT, W, REG_DI_id)
#define OP_eax AO_REGISTER(AOF_IMPLICIT, 32, REG_eax_id)
#define OP_ecx AO_REGISTER(AOF_IMPLICIT, 32, REG_ecx_id)
#define OP_edx AO_REGISTER(AOF_IMPLICIT, 32, REG_edx_id)
#define OP_ebx AO_REGISTER(AOF_IMPLICIT, 32, REG_ebx_id)
#define OP_esp AO_REGISTER(AOF_IMPLICIT, 32, REG_esp_id)
#define OP_ebp AO_REGISTER(AOF_IMPLICIT, 32, REG_ebp_id)
#define OP_esi AO_REGISTER(AOF_IMPLICIT, 32, REG_esi_id)
#define OP_edi AO_REGISTER(AOF_IMPLICIT, 32, REG_edi_id)
#define OP_st0 AO_REGISTER(AOF_IMPLICIT, 32, REG_st0_id)
#define OP_st1 AO_REGISTER(AOF_IMPLICIT, 32, REG_st1_id)
#define OP_st2 AO_REGISTER(AOF_IMPLICIT, 32, REG_st2_id)
#define OP_st3 AO_REGISTER(AOF_IMPLICIT, 32, REG_st3_id)
#define OP_st4 AO_REGISTER(AOF_IMPLICIT, 32, REG_st4_id)
#define OP_st5 AO_REGISTER(AOF_IMPLICIT, 32, REG_st5_id)
#define OP_st6 AO_REGISTER(AOF_IMPLICIT, 32, REG_st6_id)
#define OP_st7 AO_REGISTER(AOF_IMPLICIT, 32, REG_st7_id)
/* mod r/m byte */
#define AOF_I386_MODRM 0x2
#define OP_RM8_D0 AO_DREGISTER(AOF_I386_MODRM, 0, W, 0) /* 0x00 */
#define OP_RM8_D8 AO_DREGISTER(AOF_I386_MODRM, 8, W, 0) /* 0x40 */
#define OP_RM8_DW AO_DREGISTER(AOF_I386_MODRM, W, W, 0) /* 0x80 */
#define OP_RM8_R8 AO_REGISTER(AOF_I386_MODRM, 8, 0) /* 0xc0 */
#define OP_RM8_D0_R AO_DREGISTER(AOF_I386_MODRM, 0, W, 8) /* 0x00 */
#define OP_RM8_D8_R AO_DREGISTER(AOF_I386_MODRM, 8, W, 8) /* 0x40 */
#define OP_RM8_DW_R AO_DREGISTER(AOF_I386_MODRM, W, W, 8) /* 0x80 */
#define OP_RM8_R8_R AO_REGISTER(AOF_I386_MODRM, 8, 8) /* 0xc0 */
#define OP_RMW_D0 AO_DREGISTER(AOF_I386_MODRM, 0, W, 0) /* 0x00 */
#define OP_RMW_D8 AO_DREGISTER(AOF_I386_MODRM, 8, W, 0) /* 0x40 */
#define OP_RMW_DW AO_DREGISTER(AOF_I386_MODRM, W, W, 0) /* 0x80 */
#define OP_RMW_RW AO_REGISTER(AOF_I386_MODRM, W, 0) /* 0xc0 */
#define OP_RMW_D0_R AO_DREGISTER(AOF_I386_MODRM, 0, W, 8) /* 0x00 */
#define OP_RMW_D8_R AO_DREGISTER(AOF_I386_MODRM, 8, W, 8) /* 0x40 */
#define OP_RMW_DW_R AO_DREGISTER(AOF_I386_MODRM, W, W, 8) /* 0x80 */
#define OP_RMW_RW_R AO_REGISTER(AOF_I386_MODRM, W, 8) /* 0xc0 */
/* immediate values */
#define OP_S8 AO_IMMEDIATE(AOF_SIGNED, 0, 8)
#define OP_SW AO_IMMEDIATE(AOF_SIGNED, 0, W)
#define OP_U8 AO_IMMEDIATE(0, 0, 8)
#define OP_U16 AO_IMMEDIATE(0, 0, 16)
#define OP_UW AO_IMMEDIATE(0, 0, W)
/* instructions */
{ "aaa", 0x37, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
{ "aad", 0xd50a, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
{ "aad", 0xd5, OP1F, OP_U8, AOT_NONE, AOT_NONE },
{ "aam", 0xd40a, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
{ "aam", 0xd4, OP1F, OP_U8, AOT_NONE, AOT_NONE },
{ "aas", 0x3f, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
/* ADC 0x14 ib 1 al imm8 */
{ "adc", 0x14, OP1F, OP_al, OP_S8, AOT_NONE },
/* ADC 0x15 iW 1 AX immW */
{ "adc", 0x15, OP1F, OP_AX, OP_SW, AOT_NONE },
/* ADC 0x10 /r 1 r/m8 r8 */
{ "adc", 0x10, OP1F, OP_RM8_D0_R,OP_R8, AOT_NONE },
{ "adc", 0x10, OP1F, OP_RM8_D8_R,OP_R8, AOT_NONE },
{ "adc", 0x10, OP1F, OP_RM8_DW_R,OP_R8, AOT_NONE },
{ "adc", 0x10, OP1F, OP_RM8_R8_R,OP_R8, AOT_NONE },
/* ADC 0x11 /r 1 r/mW rW */
{ "adc", 0x11, OP1F, OP_RMW_D0_R,OP_RW, AOT_NONE },
{ "adc", 0x11, OP1F, OP_RMW_D8_R,OP_RW, AOT_NONE },
{ "adc", 0x11, OP1F, OP_RMW_DW_R,OP_RW, AOT_NONE },
{ "adc", 0x11, OP1F, OP_RMW_RW_R,OP_RW, AOT_NONE },
/* ADC 0x12 /r 1 r8 r/m8 */
#if 1 /* FIXME doesn't work at the moment */
{ "adc", 0x12, OP1F, OP_RM8_R8_R,OP_RM8_D0_R,AOT_NONE },
{ "adc", 0x12, OP1F, OP_RM8_R8_R,OP_RM8_D8_R,AOT_NONE },
{ "adc", 0x12, OP1F, OP_RM8_R8_R,OP_RM8_DW_R,AOT_NONE },
{ "adc", 0x12, OP1F, OP_RM8_R8_R,OP_RM8_R8_R,AOT_NONE },
#endif
/* ADC 0x13 /r 1 rW r/mW */
#if 1 /* FIXME doesn't work at the moment */
{ "adc", 0x13, OP1F, OP_RMW_RW_R,OP_RMW_D0_R,AOT_NONE },
{ "adc", 0x13, OP1F, OP_RMW_RW_R,OP_RMW_D8_R,AOT_NONE },
{ "adc", 0x13, OP1F, OP_RMW_RW_R,OP_RMW_DW_R,AOT_NONE },
{ "adc", 0x13, OP1F, OP_RMW_RW_R,OP_RMW_RW_R,AOT_NONE },
#endif
/* ADC 0x80 /2 ib 1 r/m8 imm8 */
{ "adcb", 0x80, OP1F, OP_RM8_D0+2,OP_S8, AOT_NONE },
{ "adcb", 0x80, OP1F, OP_RM8_D8+2,OP_S8, AOT_NONE },
{ "adcb", 0x80, OP1F, OP_RM8_DW+2,OP_S8, AOT_NONE },
{ "adc", 0x80, OP1F, OP_RM8_R8+2,OP_S8, AOT_NONE },
/* ADC 0x81 /2 iW 1 r/mW immW */
{ "adc", 0x81, OP1F, OP_RMW_D0+2,OP_SW, AOT_NONE },
{ "adc", 0x81, OP1F, OP_RMW_D8+2,OP_SW, AOT_NONE },
{ "adc", 0x81, OP1F, OP_RMW_DW+2,OP_SW, AOT_NONE },
{ "adc", 0x81, OP1F, OP_RMW_RW+2,OP_SW, AOT_NONE },
/* ADC 0x83 /2 ib 1 r/mW imm8 */
{ "adcb", 0x83, OP1F, OP_RMW_D0+2,OP_S8, AOT_NONE },
{ "adcb", 0x83, OP1F, OP_RMW_D8+2,OP_S8, AOT_NONE },
{ "adcb", 0x83, OP1F, OP_RMW_DW+2,OP_S8, AOT_NONE },
{ "adc", 0x83, OP1F, OP_RMW_RW+2,OP_S8, AOT_NONE },
/* ADD 0x04 ib 1 al imm8 */
{ "add", 0x04, OP1F, OP_al, OP_S8, AOT_NONE },
/* ADD 0x05 iW 1 AX immW */
{ "add", 0x05, OP1F, OP_AX, OP_SW, AOT_NONE },
/* ADD 0x00 /r 1 r/m8 r8 */
{ "add", 0x00, OP1F, OP_RM8_D0_R,OP_R8, AOT_NONE },
{ "add", 0x00, OP1F, OP_RM8_D8_R,OP_R8, AOT_NONE },
{ "add", 0x00, OP1F, OP_RM8_DW_R,OP_R8, AOT_NONE },
{ "add", 0x00, OP1F, OP_RM8_R8_R,OP_R8, AOT_NONE },
/* ADD 0x01 /r 1 r/mW rW */
{ "add", 0x01, OP1F, OP_RMW_D0_R,OP_RW, AOT_NONE },
{ "add", 0x01, OP1F, OP_RMW_D8_R,OP_RW, AOT_NONE },
{ "add", 0x01, OP1F, OP_RMW_DW_R,OP_RW, AOT_NONE },
{ "add", 0x01, OP1F, OP_RMW_RW_R,OP_RW, AOT_NONE },
/* ADD 0x02 /r 1 r8 r/m8 */
#if 1 /* FIXME probably doesn't work at the moment */
{ "add", 0x02, OP1F, OP_RM8_R8_R,OP_RM8_D0_R,AOT_NONE },
{ "add", 0x02, OP1F, OP_RM8_R8_R,OP_RM8_D8_R,AOT_NONE },
{ "add", 0x02, OP1F, OP_RM8_R8_R,OP_RM8_DW_R,AOT_NONE },
{ "add", 0x02, OP1F, OP_RM8_R8_R,OP_RM8_R8_R,AOT_NONE },
#endif
/* ADD 0x03 /r 1 rW r/mW */
#if 1 /* FIXME probably doesn't work at the moment */
{ "add", 0x03, OP1F, OP_RMW_RW_R,OP_RMW_D0_R,AOT_NONE },
{ "add", 0x03, OP1F, OP_RMW_RW_R,OP_RMW_D8_R,AOT_NONE },
{ "add", 0x03, OP1F, OP_RMW_RW_R,OP_RMW_DW_R,AOT_NONE },
{ "add", 0x03, OP1F, OP_RMW_RW_R,OP_RMW_RW_R,AOT_NONE },
#endif
/* ADD 0x80 /0 ib 1 r/m8 imm8 */
{ "addb", 0x80, OP1F, OP_RM8_D0+0,OP_S8, AOT_NONE },
{ "addb", 0x80, OP1F, OP_RM8_D8+0,OP_S8, AOT_NONE },
{ "addb", 0x80, OP1F, OP_RM8_DW+0,OP_S8, AOT_NONE },
{ "add", 0x80, OP1F, OP_RM8_R8+0,OP_S8, AOT_NONE },
/* ADD 0x81 /0 iW 1 r/mW immW */
{ "add", 0x81, OP1F, OP_RMW_D0+0,OP_SW, AOT_NONE },
{ "add", 0x81, OP1F, OP_RMW_D8+0,OP_SW, AOT_NONE },
{ "add", 0x81, OP1F, OP_RMW_DW+0,OP_SW, AOT_NONE },
{ "add", 0x81, OP1F, OP_RMW_RW+0,OP_SW, AOT_NONE },
/* ADD 0x83 /0 ib 1 r/mW imm8 */
{ "addb", 0x83, OP1F, OP_RMW_D0+0,OP_S8, AOT_NONE },
{ "addb", 0x83, OP1F, OP_RMW_D8+0,OP_S8, AOT_NONE },
{ "addb", 0x83, OP1F, OP_RMW_DW+0,OP_S8, AOT_NONE },
{ "add", 0x83, OP1F, OP_RMW_RW+0,OP_S8, AOT_NONE },
/* AND 0x24 ib 1 al imm8 */
{ "and", 0x24, OP1F, OP_al, OP_S8, AOT_NONE },
/* AND 0x25 iW 1 AX immW */
{ "and", 0x25, OP1F, OP_AX, OP_SW, AOT_NONE },
/* AND 0x20 /r 1 r/m8 r8 */
{ "and", 0x20, OP1F, OP_RM8_D0_R,OP_R8, AOT_NONE },
{ "and", 0x20, OP1F, OP_RM8_D8_R,OP_R8, AOT_NONE },
{ "and", 0x20, OP1F, OP_RM8_DW_R,OP_R8, AOT_NONE },
{ "and", 0x20, OP1F, OP_RM8_R8_R,OP_R8, AOT_NONE },
/* AND 0x21 /r 1 r/mW rW */
{ "and", 0x21, OP1F, OP_RMW_D0_R,OP_RW, AOT_NONE },
{ "and", 0x21, OP1F, OP_RMW_D8_R,OP_RW, AOT_NONE },
{ "and", 0x21, OP1F, OP_RMW_DW_R,OP_RW, AOT_NONE },
{ "and", 0x21, OP1F, OP_RMW_RW_R,OP_RW, AOT_NONE },
/* AND 0x22 /r 1 r8 r/m8 */
#if 1 /* FIXME probably doesn't work at the moment */
{ "and", 0x22, OP1F, OP_RM8_R8_R,OP_RM8_D0_R,AOT_NONE },
{ "and", 0x22, OP1F, OP_RM8_R8_R,OP_RM8_D8_R,AOT_NONE },
{ "and", 0x22, OP1F, OP_RM8_R8_R,OP_RM8_DW_R,AOT_NONE },
{ "and", 0x22, OP1F, OP_RM8_R8_R,OP_RM8_R8_R,AOT_NONE },
#endif
/* AND 0x23 /r 1 rW r/mW */
#if 1 /* FIXME probably doesn't work at the moment */
{ "and", 0x23, OP1F, OP_RMW_RW_R,OP_RMW_D0_R,AOT_NONE },
{ "and", 0x23, OP1F, OP_RMW_RW_R,OP_RMW_D8_R,AOT_NONE },
{ "and", 0x23, OP1F, OP_RMW_RW_R,OP_RMW_DW_R,AOT_NONE },
{ "and", 0x23, OP1F, OP_RMW_RW_R,OP_RMW_RW_R,AOT_NONE },
#endif
/* AND 0x80 /0 ib 1 r/m8 imm8 */
{ "andb", 0x80, OP1F, OP_RM8_D0+4,OP_S8, AOT_NONE },
{ "andb", 0x80, OP1F, OP_RM8_D8+4,OP_S8, AOT_NONE },
{ "andb", 0x80, OP1F, OP_RM8_DW+4,OP_S8, AOT_NONE },
{ "and", 0x80, OP1F, OP_RM8_R8+4,OP_S8, AOT_NONE },
/* AND 0x81 /0 iW 1 r/mW immW */
{ "and", 0x81, OP1F, OP_RMW_D0+4,OP_SW, AOT_NONE },
{ "and", 0x81, OP1F, OP_RMW_D8+4,OP_SW, AOT_NONE },
{ "and", 0x81, OP1F, OP_RMW_DW+4,OP_SW, AOT_NONE },
{ "and", 0x81, OP1F, OP_RMW_RW+4,OP_SW, AOT_NONE },
/* AND 0x83 /0 ib 1 r/mW imm8 */
{ "andb", 0x83, OP1F, OP_RMW_D0+4,OP_S8, AOT_NONE },
{ "andb", 0x83, OP1F, OP_RMW_D8+4,OP_S8, AOT_NONE },
{ "andb", 0x83, OP1F, OP_RMW_DW+4,OP_S8, AOT_NONE },
{ "and", 0x83, OP1F, OP_RMW_RW+4,OP_S8, AOT_NONE },
/* ARPL */
/* FIXME implement */
/* BOUND */
/* FIXME implement */
/* BSF 0x0fbc 2 rW r/mW */
#if 1 /* FIXME doesn't work at the moment */
{ "bsf", 0x0fbc, OP2F, OP_RMW_RW_R,OP_RMW_D0_R,AOT_NONE },
{ "bsf", 0x0fbc, OP2F, OP_RMW_RW_R,OP_RMW_D8_R,AOT_NONE },
{ "bsf", 0x0fbc, OP2F, OP_RMW_RW_R,OP_RMW_DW_R,AOT_NONE },
{ "bsf", 0x0fbc, OP2F, OP_RMW_RW_R,OP_RMW_RW_R,AOT_NONE },
#endif
/* BSR 0x0fbd 2 rW r/mW */
#if 1 /* FIXME doesn't work at the moment */
{ "bsr", 0x0fbd, OP2F, OP_RMW_RW_R,OP_RMW_D0_R,AOT_NONE },
{ "bsr", 0x0fbd, OP2F, OP_RMW_RW_R,OP_RMW_D8_R,AOT_NONE },
{ "bsr", 0x0fbd, OP2F, OP_RMW_RW_R,OP_RMW_DW_R,AOT_NONE },
{ "bsr", 0x0fbd, OP2F, OP_RMW_RW_R,OP_RMW_RW_R,AOT_NONE },
#endif
/* BT 0x0fa3 2 r/mW rW */
{ "bt", 0x0fa3, OP2F, OP_RMW_D0_R,OP_RW, AOT_NONE },
{ "bt", 0x0fa3, OP2F, OP_RMW_D8_R,OP_RW, AOT_NONE },
{ "bt", 0x0fa3, OP2F, OP_RMW_DW_R,OP_RW, AOT_NONE },
{ "bt", 0x0fa3, OP2F, OP_RMW_RW_R,OP_RW, AOT_NONE },
/* BT 0x0fba /4 ib 2 r/mW imm8 */
{ "bt", 0x0fba, OP2F, OP_RMW_D0+4,OP_S8, AOT_NONE },
{ "bt", 0x0fba, OP2F, OP_RMW_D8+4,OP_S8, AOT_NONE },
{ "bt", 0x0fba, OP2F, OP_RMW_DW+4,OP_S8, AOT_NONE },
{ "bt", 0x0fba, OP2F, OP_RMW_RW+4,OP_S8, AOT_NONE },
/* BTC 0x0fbb 2 r/mW rW */
{ "btc", 0x0fbb, OP2F, OP_RMW_D0_R,OP_RW, AOT_NONE },
{ "btc", 0x0fbb, OP2F, OP_RMW_D8_R,OP_RW, AOT_NONE },
{ "btc", 0x0fbb, OP2F, OP_RMW_DW_R,OP_RW, AOT_NONE },
{ "btc", 0x0fbb, OP2F, OP_RMW_RW_R,OP_RW, AOT_NONE },
/* BTC 0x0fba /7 ib 2 r/mW imm8 */
{ "btc", 0x0fba, OP2F, OP_RMW_D0+7,OP_S8, AOT_NONE },
{ "btc", 0x0fba, OP2F, OP_RMW_D8+7,OP_S8, AOT_NONE },
{ "btc", 0x0fba, OP2F, OP_RMW_DW+7,OP_S8, AOT_NONE },
{ "btc", 0x0fba, OP2F, OP_RMW_RW+7,OP_S8, AOT_NONE },
/* BTR 0x0fb3 2 r/mW rW */
{ "btr", 0x0fb3, OP2F, OP_RMW_D0_R,OP_RW, AOT_NONE },
{ "btr", 0x0fb3, OP2F, OP_RMW_D8_R,OP_RW, AOT_NONE },
{ "btr", 0x0fb3, OP2F, OP_RMW_DW_R,OP_RW, AOT_NONE },
{ "btr", 0x0fb3, OP2F, OP_RMW_RW_R,OP_RW, AOT_NONE },
/* BTR 0x0fba /6 ib 2 r/mW imm8 */
{ "btr", 0x0fba, OP2F, OP_RMW_D0+6,OP_S8, AOT_NONE },
{ "btr", 0x0fba, OP2F, OP_RMW_D8+6,OP_S8, AOT_NONE },
{ "btr", 0x0fba, OP2F, OP_RMW_DW+6,OP_S8, AOT_NONE },
{ "btr", 0x0fba, OP2F, OP_RMW_RW+6,OP_S8, AOT_NONE },
/* BTS 0x0fab 2 r/mW rW */
{ "bts", 0x0fab, OP2F, OP_RMW_D0_R,OP_RW, AOT_NONE },
{ "bts", 0x0fab, OP2F, OP_RMW_D8_R,OP_RW, AOT_NONE },
{ "bts", 0x0fab, OP2F, OP_RMW_DW_R,OP_RW, AOT_NONE },
{ "bts", 0x0fab, OP2F, OP_RMW_RW_R,OP_RW, AOT_NONE },
/* BTS 0x0fba /5 ib 2 r/mW imm8 */
{ "bts", 0x0fba, OP2F, OP_RMW_D0+5,OP_S8, AOT_NONE },
{ "bts", 0x0fba, OP2F, OP_RMW_D8+5,OP_S8, AOT_NONE },
{ "bts", 0x0fba, OP2F, OP_RMW_DW+5,OP_S8, AOT_NONE },
{ "bts", 0x0fba, OP2F, OP_RMW_RW+5,OP_S8, AOT_NONE },
/* CALL */
/* FIXME implement */
#if defined(ARCH_i386_real)
/* CBW 0x98 1 */
{ "cbw", 0x98, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
#else
/* CWDE 0x98 1 */
{ "cwde", 0x98, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
#endif
/* CLC 0xf8 1 */
{ "clc", 0xf8, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
/* CLD 0xfc 1 */
{ "cld", 0xfc, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
/* CLI 0xfa 1 */
{ "cli", 0xfa, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
/* CLTS 0xfa 2 */
{ "clts", 0x0f06, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
/* CMC 0xf5 1 */
{ "cmc", 0xf5, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
/* CMOVcc */
/* FIXME implement */
/* CMP */
/* FIXME implement */
/* CPUID 0x0fa2 2 */
{ "cpuid", 0x0fa2, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
#if defined(ARCH_i386_real)
/* CWD 0x99 1 */
{ "cwd", 0x99, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
#else
/* CDQ 0x99 1 */
{ "cdq", 0x99, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
#endif
/* DAA 0x27 1 */
{ "daa", 0x27, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
/* DAS 0x2f 1 */
{ "das", 0x2f, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
/* DEC 0x48 +rd 1 */
{ "dec", 0x48, OP1F, OP_AX, AOT_NONE, AOT_NONE },
{ "dec", 0x49, OP1F, OP_CX, AOT_NONE, AOT_NONE },
{ "dec", 0x4a, OP1F, OP_DX, AOT_NONE, AOT_NONE },
{ "dec", 0x4b, OP1F, OP_BX, AOT_NONE, AOT_NONE },
{ "dec", 0x4c, OP1F, OP_SP, AOT_NONE, AOT_NONE },
{ "dec", 0x4d, OP1F, OP_BP, AOT_NONE, AOT_NONE },
{ "dec", 0x4e, OP1F, OP_SI, AOT_NONE, AOT_NONE },
{ "dec", 0x4f, OP1F, OP_DI, AOT_NONE, AOT_NONE },
/* DEC 0xfe /1 1 r/m8 */
{ "decb", 0xfe, OP1F, OP_RM8_D0+1,AOT_NONE, AOT_NONE },
{ "decb", 0xfe, OP1F, OP_RM8_D8+1,AOT_NONE, AOT_NONE },
{ "decb", 0xfe, OP1F, OP_RM8_DW+1,AOT_NONE, AOT_NONE },
{ "dec", 0xfe, OP1F, OP_RM8_R8+1,AOT_NONE, AOT_NONE },
/* DEC 0xff /1 1 r/mW */
{ "dec", 0xff, OP1F, OP_RMW_D0+1,AOT_NONE, AOT_NONE },
{ "dec", 0xff, OP1F, OP_RMW_D8+1,AOT_NONE, AOT_NONE },
{ "dec", 0xff, OP1F, OP_RMW_DW+1,AOT_NONE, AOT_NONE },
{ "dec", 0xff, OP1F, OP_RMW_RW+1,AOT_NONE, AOT_NONE },
/* DIV 0xf6 /6 1 r/m8 */
{ "divb", 0xf6, OP1F, OP_RM8_D0+6,AOT_NONE, AOT_NONE },
{ "divb", 0xf6, OP1F, OP_RM8_D8+6,AOT_NONE, AOT_NONE },
{ "divb", 0xf6, OP1F, OP_RM8_DW+6,AOT_NONE, AOT_NONE },
{ "div", 0xf6, OP1F, OP_RM8_R8+6,AOT_NONE, AOT_NONE },
/* DIV 0xf7 /6 1 r/mW */
{ "div", 0xf7, OP1F, OP_RMW_D0+6,AOT_NONE, AOT_NONE },
{ "div", 0xf7, OP1F, OP_RMW_D8+6,AOT_NONE, AOT_NONE },
{ "div", 0xf7, OP1F, OP_RMW_DW+6,AOT_NONE, AOT_NONE },
{ "div", 0xf7, OP1F, OP_RMW_RW+6,AOT_NONE, AOT_NONE },
/* ENTER 0xc8 iw 1 imm16 imm8 */
{ "enter", 0xc8, OP1F, OP_U16, OP_U8, AOT_NONE },
/* F2XM1 0xd9f0 2 */
{ "f2xm1", 0xd9f0, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
/* FABS 0xd9e1 2 */
{ "fabs", 0xd9e1, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
/* FADD 0xd8 /0 1 m32real */
/* FIXME implement */
/* FADD 0xdc /0 1 m64real */
/* FIXME implement */
/* FADD 0xd8c0 +i 2 st(0) st(i) */
{ "fadd", 0xd8c0, OP2F, OP_st0, OP_st0, AOT_NONE },
{ "fadd", 0xd8c1, OP2F, OP_st0, OP_st1, AOT_NONE },
{ "fadd", 0xd8c2, OP2F, OP_st0, OP_st2, AOT_NONE },
{ "fadd", 0xd8c3, OP2F, OP_st0, OP_st3, AOT_NONE },
{ "fadd", 0xd8c4, OP2F, OP_st0, OP_st4, AOT_NONE },
{ "fadd", 0xd8c5, OP2F, OP_st0, OP_st5, AOT_NONE },
{ "fadd", 0xd8c6, OP2F, OP_st0, OP_st6, AOT_NONE },
{ "fadd", 0xd8c7, OP2F, OP_st0, OP_st7, AOT_NONE },
/* FADD 0xdcc0 +i 2 st(i) st(0) */
{ "fadd", 0xdcc0, OP2F, OP_st0, OP_st0, AOT_NONE },
{ "fadd", 0xdcc1, OP2F, OP_st1, OP_st0, AOT_NONE },
{ "fadd", 0xdcc2, OP2F, OP_st2, OP_st0, AOT_NONE },
{ "fadd", 0xdcc3, OP2F, OP_st3, OP_st0, AOT_NONE },
{ "fadd", 0xdcc4, OP2F, OP_st4, OP_st0, AOT_NONE },
{ "fadd", 0xdcc5, OP2F, OP_st5, OP_st0, AOT_NONE },
{ "fadd", 0xdcc6, OP2F, OP_st6, OP_st0, AOT_NONE },
{ "fadd", 0xdcc7, OP2F, OP_st7, OP_st0, AOT_NONE },
/* FADDP 0xdec1 2 */
{ "faddp", 0xdec1, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
/* FADDP 0xdec0 +i 2 st(i) st(0) */
{ "faddp", 0xdec0, OP2F, OP_st0, OP_st0, AOT_NONE },
{ "faddp", 0xdec1, OP2F, OP_st1, OP_st0, AOT_NONE },
{ "faddp", 0xdec2, OP2F, OP_st2, OP_st0, AOT_NONE },
{ "faddp", 0xdec3, OP2F, OP_st3, OP_st0, AOT_NONE },
{ "faddp", 0xdec4, OP2F, OP_st4, OP_st0, AOT_NONE },
{ "faddp", 0xdec5, OP2F, OP_st5, OP_st0, AOT_NONE },
{ "faddp", 0xdec6, OP2F, OP_st6, OP_st0, AOT_NONE },
{ "faddp", 0xdec7, OP2F, OP_st7, OP_st0, AOT_NONE },
/* FBLD 0xdf /4 1 m80dec */
/* FIXME implement */
/* FBSTP 0xdf /6 1 m80bcd */
/* FIXME implement */
/* FCHS 0xd9e0 2 */
{ "fchs", 0xd9e0, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
/* FCLEX 0x9bdbe2 3 */
{ "fclex", 0x9bdbe2, OP3F, AOT_NONE, AOT_NONE, AOT_NONE },
/* FCMOVcc */
/* FIXME implement */
/* FIADD 0xda /0 1 m32int */
/* FIXME implement */
/* FIADD 0xde /0 1 m64int */
/* FIXME implement */
/* FNCLEX 0xdbe2 2 */
{ "fnclex", 0xdbe2, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
/* FWAIT 0x9b 1 */
{ "fwait", 0x9b, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
/* NOP 0x90 1 */
{ "nop", 0x90, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
/* SUB 0x2c ib 1 al imm8 */
{ "sub", 0x2c, OP1F, OP_al, OP_S8, AOT_NONE },
/* SUB 0x2d iW 1 AX immW */
{ "sub", 0x2d, OP1F, OP_AX, OP_SW, AOT_NONE },
/* SUB 0x28 /r 1 r/m8 r8 */
{ "sub", 0x28, OP1F, OP_RM8_D0_R,OP_R8, AOT_NONE },
{ "sub", 0x28, OP1F, OP_RM8_D8_R,OP_R8, AOT_NONE },
{ "sub", 0x28, OP1F, OP_RM8_DW_R,OP_R8, AOT_NONE },
{ "sub", 0x28, OP1F, OP_RM8_R8_R,OP_R8, AOT_NONE },
/* SUB 0x29 /r 1 r/mW rW */
{ "sub", 0x29, OP1F, OP_RMW_D0_R,OP_RW, AOT_NONE },
{ "sub", 0x29, OP1F, OP_RMW_D8_R,OP_RW, AOT_NONE },
{ "sub", 0x29, OP1F, OP_RMW_DW_R,OP_RW, AOT_NONE },
{ "sub", 0x29, OP1F, OP_RMW_RW_R,OP_RW, AOT_NONE },
/* SUB 0x2a /r 1 r8 r/m8 */
#if 1 /* FIXME probably doesn't work at the moment */
{ "sub", 0x2a, OP1F, OP_RM8_R8_R,OP_RM8_D0_R,AOT_NONE },
{ "sub", 0x2a, OP1F, OP_RM8_R8_R,OP_RM8_D8_R,AOT_NONE },
{ "sub", 0x2a, OP1F, OP_RM8_R8_R,OP_RM8_DW_R,AOT_NONE },
{ "sub", 0x2a, OP1F, OP_RM8_R8_R,OP_RM8_R8_R,AOT_NONE },
#endif
/* SUB 0x2b /r 1 rW r/mW */
#if 1 /* FIXME probably doesn't work at the moment */
{ "sub", 0x2b, OP1F, OP_RMW_RW_R,OP_RMW_D0_R,AOT_NONE },
{ "sub", 0x2b, OP1F, OP_RMW_RW_R,OP_RMW_D8_R,AOT_NONE },
{ "sub", 0x2b, OP1F, OP_RMW_RW_R,OP_RMW_DW_R,AOT_NONE },
{ "sub", 0x2b, OP1F, OP_RMW_RW_R,OP_RMW_RW_R,AOT_NONE },
#endif
/* SUB 0x80 /5 ib 1 r/m8 imm8 */
{ "subb", 0x80, OP1F, OP_RM8_D0+5,OP_S8, AOT_NONE },
{ "subb", 0x80, OP1F, OP_RM8_D8+5,OP_S8, AOT_NONE },
{ "subb", 0x80, OP1F, OP_RM8_DW+5,OP_S8, AOT_NONE },
{ "sub", 0x80, OP1F, OP_RM8_R8+5,OP_S8, AOT_NONE },
/* SUB 0x81 /5 iW 1 r/mW immW */
{ "sub", 0x81, OP1F, OP_RMW_D0+5,OP_SW, AOT_NONE },
{ "sub", 0x81, OP1F, OP_RMW_D8+5,OP_SW, AOT_NONE },
{ "sub", 0x81, OP1F, OP_RMW_DW+5,OP_SW, AOT_NONE },
{ "sub", 0x81, OP1F, OP_RMW_RW+5,OP_SW, AOT_NONE },
/* SUB 0x83 /5 ib 1 r/mW imm8 */
{ "subb", 0x83, OP1F, OP_RMW_D0+5,OP_S8, AOT_NONE },
{ "subb", 0x83, OP1F, OP_RMW_D8+5,OP_S8, AOT_NONE },
{ "subb", 0x83, OP1F, OP_RMW_DW+5,OP_S8, AOT_NONE },
{ "sub", 0x83, OP1F, OP_RMW_RW+5,OP_S8, AOT_NONE },
/* TEST 0xa8 ib 1 al imm8 */
{ "test", 0xa8, OP1F, OP_al, OP_S8, AOT_NONE },
/* TEST 0xa9 iW 1 AX immW */
{ "test", 0xa9, OP1F, OP_AX, OP_SW, AOT_NONE },
/* TEST 0xf6 /0 ib 1 r/m8 imm8 */
{ "testb", 0xf6, OP1F, OP_RM8_D0+0,OP_S8, AOT_NONE },
{ "testb", 0xf6, OP1F, OP_RM8_D8+0,OP_S8, AOT_NONE },
{ "testb", 0xf6, OP1F, OP_RM8_DW+0,OP_S8, AOT_NONE },
{ "test", 0xf6, OP1F, OP_RM8_R8+0,OP_S8, AOT_NONE },
/* TEST 0xf7 /0 iW 1 r/mW immW */
{ "test", 0xf7, OP1F, OP_RMW_D0+0,OP_SW, AOT_NONE },
{ "test", 0xf7, OP1F, OP_RMW_D8+0,OP_SW, AOT_NONE },
{ "test", 0xf7, OP1F, OP_RMW_DW+0,OP_SW, AOT_NONE },
{ "test", 0xf7, OP1F, OP_RMW_RW+0,OP_SW, AOT_NONE },
/* TEST 0x84 1 r/m8 r8 */
#if 1 /* FIXME doesn't work */
{ "testb", 0x84, OP1F, OP_RM8_D0, OP_R8, AOT_NONE },
{ "testb", 0x84, OP1F, OP_RM8_D8, OP_R8, AOT_NONE },
{ "testb", 0x84, OP1F, OP_RM8_DW, OP_R8, AOT_NONE },
{ "test", 0x84, OP1F, OP_RM8_R8, OP_R8, AOT_NONE },
#endif
/* TEST 0x85 1 r/mW rW */
#if 1 /* FIXME doesn't work */
{ "test", 0x85, OP1F, OP_RMW_D0, OP_RW, AOT_NONE },
{ "test", 0x85, OP1F, OP_RMW_D8, OP_RW, AOT_NONE },
{ "test", 0x85, OP1F, OP_RMW_DW, OP_RW, AOT_NONE },
{ "test", 0x85, OP1F, OP_RMW_RW, OP_RW, AOT_NONE },
#endif
/* UD2 0x0f0b 2 */
{ "ud2", 0x0f0b, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
/* VERR 0x0f00 /4 2 r/m16 */
/* FIXME implement */
/* VERW 0x0f00 /5 2 r/m16 */
/* FIXME implement */
/* WAIT 0x9b 1 */
{ "wait", 0x9b, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
/* WBINVD 0x0f09 2 */
{ "wbinvd", 0x0f09, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
/* WRMSR 0x0f30 2 */
{ "wrmsr", 0x0f30, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
/* XADD 0x0fc0 /r 2 r/m8 r8 */
{ "xadd", 0x0fc0, OP2F, OP_RM8_D0_R,OP_R8, AOT_NONE },
{ "xadd", 0x0fc0, OP2F, OP_RM8_D8_R,OP_R8, AOT_NONE },
{ "xadd", 0x0fc0, OP2F, OP_RM8_DW_R,OP_R8, AOT_NONE },
{ "xadd", 0x0fc0, OP2F, OP_RM8_R8_R,OP_R8, AOT_NONE },
/* XADD 0x0fc1 /r 2 r/mW rW */
{ "xadd", 0x0fc1, OP2F, OP_RMW_D0_R,OP_RW, AOT_NONE },
{ "xadd", 0x0fc1, OP2F, OP_RMW_D8_R,OP_RW, AOT_NONE },
{ "xadd", 0x0fc1, OP2F, OP_RMW_DW_R,OP_RW, AOT_NONE },
{ "xadd", 0x0fc1, OP2F, OP_RMW_RW_R,OP_RW, AOT_NONE },
/* XCHG 0x90 +rW 1 AX rW */
{ "xchg", 0x90, OP1F, OP_AX, OP_AX, AOT_NONE },
{ "xchg", 0x91, OP1F, OP_AX, OP_CX, AOT_NONE },
{ "xchg", 0x92, OP1F, OP_AX, OP_DX, AOT_NONE },
{ "xchg", 0x93, OP1F, OP_AX, OP_BX, AOT_NONE },
{ "xchg", 0x94, OP1F, OP_AX, OP_SP, AOT_NONE },
{ "xchg", 0x95, OP1F, OP_AX, OP_BP, AOT_NONE },
{ "xchg", 0x96, OP1F, OP_AX, OP_SI, AOT_NONE },
{ "xchg", 0x97, OP1F, OP_AX, OP_DI, AOT_NONE },
{ "xchg", 0x91, OP1F, OP_CX, OP_AX, AOT_NONE },
{ "xchg", 0x92, OP1F, OP_DX, OP_AX, AOT_NONE },
{ "xchg", 0x93, OP1F, OP_BX, OP_AX, AOT_NONE },
{ "xchg", 0x94, OP1F, OP_SP, OP_AX, AOT_NONE },
{ "xchg", 0x95, OP1F, OP_BP, OP_AX, AOT_NONE },
{ "xchg", 0x96, OP1F, OP_SI, OP_AX, AOT_NONE },
{ "xchg", 0x97, OP1F, OP_DI, OP_AX, AOT_NONE },
/* XCHG 0x86 /r 1 r/m8 r8 */
{ "xchg", 0x86, OP1F, OP_RM8_D0_R,OP_R8, AOT_NONE },
{ "xchg", 0x86, OP1F, OP_RM8_D8_R,OP_R8, AOT_NONE },
{ "xchg", 0x86, OP1F, OP_RM8_DW_R,OP_R8, AOT_NONE },
{ "xchg", 0x86, OP1F, OP_RM8_R8_R,OP_R8, AOT_NONE },
/* XCHG 0x86 /r 1 r8 r/m8 */
#if 1 /* FIXME doesn't work at the moment */
{ "xchg", 0x86, OP1F, OP_RM8_R8_R,OP_RM8_D0_R,AOT_NONE },
{ "xchg", 0x86, OP1F, OP_RM8_R8_R,OP_RM8_D8_R,AOT_NONE },
{ "xchg", 0x86, OP1F, OP_RM8_R8_R,OP_RM8_DW_R,AOT_NONE },
{ "xchg", 0x86, OP1F, OP_RM8_R8_R,OP_RM8_R8_R,AOT_NONE },
#endif
/* XCHG 0x87 /r 1 r/mW rW */
{ "xchg", 0x87, OP1F, OP_RMW_D0_R,OP_RW, AOT_NONE },
{ "xchg", 0x87, OP1F, OP_RMW_D8_R,OP_RW, AOT_NONE },
{ "xchg", 0x87, OP1F, OP_RMW_DW_R,OP_RW, AOT_NONE },
{ "xchg", 0x87, OP1F, OP_RMW_RW_R,OP_RW, AOT_NONE },
/* XCHG 0x87 /r 1 rW r/mW */
#if 1 /* FIXME doesn't work at the moment */
{ "xchg", 0x87, OP1F, OP_RMW_RW_R,OP_RMW_D0_R,AOT_NONE },
{ "xchg", 0x87, OP1F, OP_RMW_RW_R,OP_RMW_D8_R,AOT_NONE },
{ "xchg", 0x87, OP1F, OP_RMW_RW_R,OP_RMW_DW_R,AOT_NONE },
{ "xchg", 0x87, OP1F, OP_RMW_RW_R,OP_RMW_RW_R,AOT_NONE },
#endif
/* XLAT 0xd7 1 */
{ "xlat", 0xd7, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
/* XLATB 0xd7 1 */
{ "xlatb", 0xd7, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
/* XOR 0x34 ib 1 al imm8 */
{ "xor", 0x34, OP1F, OP_al, OP_S8, AOT_NONE },
/* XOR 0x35 iW 1 AX immW */
{ "xor", 0x35, OP1F, OP_AX, OP_SW, AOT_NONE },
/* XOR 0x30 /r 1 r/m8 r8 */
{ "xor", 0x30, OP1F, OP_RM8_D0_R,OP_R8, AOT_NONE },
{ "xor", 0x30, OP1F, OP_RM8_D8_R,OP_R8, AOT_NONE },
{ "xor", 0x30, OP1F, OP_RM8_DW_R,OP_R8, AOT_NONE },
{ "xor", 0x30, OP1F, OP_RM8_R8_R,OP_R8, AOT_NONE },
/* XOR 0x31 /r 1 r/mW rW */
{ "xor", 0x31, OP1F, OP_RMW_D0_R,OP_RW, AOT_NONE },
{ "xor", 0x31, OP1F, OP_RMW_D8_R,OP_RW, AOT_NONE },
{ "xor", 0x31, OP1F, OP_RMW_DW_R,OP_RW, AOT_NONE },
{ "xor", 0x31, OP1F, OP_RMW_RW_R,OP_RW, AOT_NONE },
/* XOR 0x32 /r 1 r8 r/m8 */
#if 1 /* FIXME doesn't work at the moment */
{ "xor", 0x32, OP1F, OP_RM8_R8_R,OP_RM8_D0_R,AOT_NONE },
{ "xor", 0x32, OP1F, OP_RM8_R8_R,OP_RM8_D8_R,AOT_NONE },
{ "xor", 0x32, OP1F, OP_RM8_R8_R,OP_RM8_DW_R,AOT_NONE },
{ "xor", 0x32, OP1F, OP_RM8_R8_R,OP_RM8_R8_R,AOT_NONE },
#endif
/* XOR 0x33 /r 1 rW r/mW */
#if 1 /* FIXME doesn't work at the moment */
{ "xor", 0x33, OP1F, OP_RMW_RW_R,OP_RMW_D0_R,AOT_NONE },
{ "xor", 0x33, OP1F, OP_RMW_RW_R,OP_RMW_D8_R,AOT_NONE },
{ "xor", 0x33, OP1F, OP_RMW_RW_R,OP_RMW_DW_R,AOT_NONE },
{ "xor", 0x33, OP1F, OP_RMW_RW_R,OP_RMW_RW_R,AOT_NONE },
#endif
/* XOR 0x80 /6 ib 1 r/m8 imm8 */
{ "xorb", 0x80, OP1F, OP_RM8_D0+6,OP_S8, AOT_NONE },
{ "xorb", 0x80, OP1F, OP_RM8_D8+6,OP_S8, AOT_NONE },
{ "xorb", 0x80, OP1F, OP_RM8_DW+6,OP_S8, AOT_NONE },
{ "xor", 0x80, OP1F, OP_RM8_R8+6,OP_S8, AOT_NONE },
/* XOR 0x81 /6 iW 1 r/mW immW */
{ "xor", 0x81, OP1F, OP_RMW_D0+6,OP_SW, AOT_NONE },
{ "xor", 0x81, OP1F, OP_RMW_D8+6,OP_SW, AOT_NONE },
{ "xor", 0x81, OP1F, OP_RMW_DW+6,OP_SW, AOT_NONE },
{ "xor", 0x81, OP1F, OP_RMW_RW+6,OP_SW, AOT_NONE },
/* XOR 0x83 /6 ib 1 r/mW imm8 */
{ "xorb", 0x83, OP1F, OP_RMW_D0+6,OP_S8, AOT_NONE },
{ "xorb", 0x83, OP1F, OP_RMW_D8+6,OP_S8, AOT_NONE },
{ "xorb", 0x83, OP1F, OP_RMW_DW+6,OP_S8, AOT_NONE },
{ "xor", 0x83, OP1F, OP_RMW_RW+6,OP_S8, AOT_NONE },
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