1286 lines
60 KiB
TeX
1286 lines
60 KiB
TeX
/* $Id$ */
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/* Copyright (c) 2011 Pierre Pronchery <khorben@defora.org> */
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/* This file is part of DeforaOS Devel asm */
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/* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* platform-specific */
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#if defined(ARCH_i386_real) /* i386 in real mode */
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# define W 16
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# define REG_AX_id REG_ax_id
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# define REG_CX_id REG_cx_id
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# define REG_DX_id REG_dx_id
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# define REG_BX_id REG_bx_id
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# define REG_SP_id REG_sp_id
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# define REG_BP_id REG_bp_id
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# define REG_SI_id REG_si_id
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# define REG_DI_id REG_di_id
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#else /* i386 and compatible in 32-bit protected mode */
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# define W 32
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# define REG_AX_id REG_eax_id
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# define REG_CX_id REG_ecx_id
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# define REG_DX_id REG_edx_id
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# define REG_BX_id REG_ebx_id
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# define REG_SP_id REG_esp_id
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# define REG_BP_id REG_ebp_id
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# define REG_SI_id REG_esi_id
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# define REG_DI_id REG_edi_id
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#endif
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/* helpers */
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/* opcodes */
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#define OP1F (8 << AOD_SIZE)
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#define OP2F (16 << AOD_SIZE)
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#define OP3F (24 << AOD_SIZE)
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/* operands */
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/* registers */
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#define OP_R8 AO_REGISTER(0, 8, 0)
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#define OP_RW AO_REGISTER(0, W, 0)
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#define OP_al AO_REGISTER(AOF_IMPLICIT, REG_al_size, REG_al_id)
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#define OP_cl AO_REGISTER(AOF_IMPLICIT, REG_cl_size, REG_cl_id)
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#define OP_dl AO_REGISTER(AOF_IMPLICIT, REG_dl_size, REG_dl_id)
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#define OP_bl AO_REGISTER(AOF_IMPLICIT, REG_bl_size, REG_bl_id)
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#define OP_ah AO_REGISTER(AOF_IMPLICIT, REG_ah_size, REG_ah_id)
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#define OP_ch AO_REGISTER(AOF_IMPLICIT, REG_ch_size, REG_ch_id)
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#define OP_dh AO_REGISTER(AOF_IMPLICIT, REG_dh_size, REG_dh_id)
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#define OP_bh AO_REGISTER(AOF_IMPLICIT, REG_bh_size, REG_bh_id)
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#define OP_cs AO_REGISTER(AOF_IMPLICIT, REG_cs_size, REG_cs_id)
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#define OP_ds AO_REGISTER(AOF_IMPLICIT, REG_ds_size, REG_ds_id)
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#define OP_es AO_REGISTER(AOF_IMPLICIT, REG_es_size, REG_es_id)
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#define OP_fs AO_REGISTER(AOF_IMPLICIT, REG_fs_size, REG_fs_id)
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#define OP_gs AO_REGISTER(AOF_IMPLICIT, REG_gs_size, REG_gs_id)
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#define OP_ss AO_REGISTER(AOF_IMPLICIT, REG_ss_size, REG_ss_id)
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#define OP_dx AO_REGISTER(AOF_IMPLICIT, 16, REG_dx_id)
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#define OP_AX AO_REGISTER(AOF_IMPLICIT, W, REG_AX_id)
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#define OP_CX AO_REGISTER(AOF_IMPLICIT, W, REG_CX_id)
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#define OP_DX AO_REGISTER(AOF_IMPLICIT, W, REG_DX_id)
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#define OP_BX AO_REGISTER(AOF_IMPLICIT, W, REG_BX_id)
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#define OP_SP AO_REGISTER(AOF_IMPLICIT, W, REG_SP_id)
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#define OP_BP AO_REGISTER(AOF_IMPLICIT, W, REG_BP_id)
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#define OP_SI AO_REGISTER(AOF_IMPLICIT, W, REG_SI_id)
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#define OP_DI AO_REGISTER(AOF_IMPLICIT, W, REG_DI_id)
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#define OP_eax AO_REGISTER(AOF_IMPLICIT, 32, REG_eax_id)
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#define OP_ecx AO_REGISTER(AOF_IMPLICIT, 32, REG_ecx_id)
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#define OP_edx AO_REGISTER(AOF_IMPLICIT, 32, REG_edx_id)
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#define OP_ebx AO_REGISTER(AOF_IMPLICIT, 32, REG_ebx_id)
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#define OP_esp AO_REGISTER(AOF_IMPLICIT, 32, REG_esp_id)
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#define OP_ebp AO_REGISTER(AOF_IMPLICIT, 32, REG_ebp_id)
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#define OP_esi AO_REGISTER(AOF_IMPLICIT, 32, REG_esi_id)
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#define OP_edi AO_REGISTER(AOF_IMPLICIT, 32, REG_edi_id)
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#define OP_cr0 AO_REGISTER(AOF_IMPLICIT, 32, REG_cr0_id)
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#define OP_cr1 AO_REGISTER(AOF_IMPLICIT, 32, REG_cr1_id)
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#define OP_cr2 AO_REGISTER(AOF_IMPLICIT, 32, REG_cr2_id)
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#define OP_cr3 AO_REGISTER(AOF_IMPLICIT, 32, REG_cr3_id)
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#define OP_cr4 AO_REGISTER(AOF_IMPLICIT, 32, REG_cr4_id)
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#define OP_cr5 AO_REGISTER(AOF_IMPLICIT, 32, REG_cr5_id)
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#define OP_cr6 AO_REGISTER(AOF_IMPLICIT, 32, REG_cr6_id)
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#define OP_cr7 AO_REGISTER(AOF_IMPLICIT, 32, REG_cr7_id)
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#define OP_st0 AO_REGISTER(AOF_IMPLICIT, 32, REG_st0_id)
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#define OP_st1 AO_REGISTER(AOF_IMPLICIT, 32, REG_st1_id)
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#define OP_st2 AO_REGISTER(AOF_IMPLICIT, 32, REG_st2_id)
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#define OP_st3 AO_REGISTER(AOF_IMPLICIT, 32, REG_st3_id)
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#define OP_st4 AO_REGISTER(AOF_IMPLICIT, 32, REG_st4_id)
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#define OP_st5 AO_REGISTER(AOF_IMPLICIT, 32, REG_st5_id)
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#define OP_st6 AO_REGISTER(AOF_IMPLICIT, 32, REG_st6_id)
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#define OP_st7 AO_REGISTER(AOF_IMPLICIT, 32, REG_st7_id)
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/* mod r/m byte */
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#define AOF_I386_MODRM 0x2
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#define OP_R8_R AO_REGISTER(AOF_I386_MODRM, 8, 0)
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#define OP_RW_R AO_REGISTER(AOF_I386_MODRM, W, 0)
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#define OP_RM8_D0 AO_DREGISTER(AOF_I386_MODRM, 0, W, 0) /* 0x00 */
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#define OP_RM8_D8 AO_DREGISTER(AOF_I386_MODRM, 8, W, 0) /* 0x40 */
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#define OP_RM8_DW AO_DREGISTER(AOF_I386_MODRM, W, W, 0) /* 0x80 */
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#define OP_RM8_R8 AO_REGISTER(AOF_I386_MODRM, 8, 0) /* 0xc0 */
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#define OP_RM8_D0_R AO_DREGISTER(AOF_I386_MODRM, 0, W, 8) /* 0x00 */
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#define OP_RM8_D8_R AO_DREGISTER(AOF_I386_MODRM, 8, W, 8) /* 0x40 */
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#define OP_RM8_DW_R AO_DREGISTER(AOF_I386_MODRM, W, W, 8) /* 0x80 */
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#define OP_RM8_R8_R AO_REGISTER(AOF_I386_MODRM, 8, 8) /* 0xc0 */
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#define OP_RMW_D0 AO_DREGISTER(AOF_I386_MODRM, 0, W, 0) /* 0x00 */
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#define OP_RMW_D8 AO_DREGISTER(AOF_I386_MODRM, 8, W, 0) /* 0x40 */
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#define OP_RMW_DW AO_DREGISTER(AOF_I386_MODRM, W, W, 0) /* 0x80 */
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#define OP_RMW_RW AO_REGISTER(AOF_I386_MODRM, W, 0) /* 0xc0 */
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#define OP_RMW_D0_R AO_DREGISTER(AOF_I386_MODRM, 0, W, 8) /* 0x00 */
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#define OP_RMW_D8_R AO_DREGISTER(AOF_I386_MODRM, 8, W, 8) /* 0x40 */
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#define OP_RMW_DW_R AO_DREGISTER(AOF_I386_MODRM, W, W, 8) /* 0x80 */
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#define OP_RMW_RW_R AO_REGISTER(AOF_I386_MODRM, W, 8) /* 0xc0 */
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/* constant values */
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#define OP_C3 AO_CONSTANT(AOF_IMPLICIT, 8, 0x03)
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/* immediate values */
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#define OP_S8 AO_IMMEDIATE(AOF_SIGNED, 0, 8)
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#define OP_SW AO_IMMEDIATE(AOF_SIGNED, 0, W)
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#define OP_U8 AO_IMMEDIATE(0, 0, 8)
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#define OP_U16 AO_IMMEDIATE(0, 0, 16)
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#define OP_UW AO_IMMEDIATE(0, 0, W)
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/* instructions */
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#ifndef ARCH_amd64
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{ "aaa", 0x37, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
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#endif
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{ "aad", 0xd50a, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "aad", 0xd5, OP1F, OP_U8, AOT_NONE, AOT_NONE },
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{ "aam", 0xd40a, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "aam", 0xd4, OP1F, OP_U8, AOT_NONE, AOT_NONE },
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#ifndef ARCH_amd64
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{ "aas", 0x3f, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
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#endif
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/* ADC 0x14 ib 1 al imm8 */
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{ "adc", 0x14, OP1F, OP_al, OP_S8, AOT_NONE },
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/* ADC 0x15 iW 1 AX immW */
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{ "adc", 0x15, OP1F, OP_AX, OP_SW, AOT_NONE },
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/* ADC 0x10 /r 1 r/m8 r8 */
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{ "adc", 0x10, OP1F, OP_RM8_D0, OP_R8_R, AOT_NONE },
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{ "adc", 0x10, OP1F, OP_RM8_D8, OP_R8_R, AOT_NONE },
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{ "adc", 0x10, OP1F, OP_RM8_DW, OP_R8_R, AOT_NONE },
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{ "adc", 0x10, OP1F, OP_RM8_R8, OP_R8_R, AOT_NONE },
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/* ADC 0x11 /r 1 r/mW rW */
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{ "adc", 0x11, OP1F, OP_RMW_D0, OP_RW_R, AOT_NONE },
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{ "adc", 0x11, OP1F, OP_RMW_D8, OP_RW_R, AOT_NONE },
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{ "adc", 0x11, OP1F, OP_RMW_DW, OP_RW_R, AOT_NONE },
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{ "adc", 0x11, OP1F, OP_RMW_RW, OP_RW_R, AOT_NONE },
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/* ADC 0x12 /r 1 r8 r/m8 */
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#if 1 /* FIXME doesn't work at the moment */
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{ "adc", 0x12, OP1F, OP_RM8_R8_R,OP_RM8_D0_R,AOT_NONE },
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{ "adc", 0x12, OP1F, OP_RM8_R8_R,OP_RM8_D8_R,AOT_NONE },
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{ "adc", 0x12, OP1F, OP_RM8_R8_R,OP_RM8_DW_R,AOT_NONE },
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{ "adc", 0x12, OP1F, OP_RM8_R8_R,OP_RM8_R8_R,AOT_NONE },
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#endif
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/* ADC 0x13 /r 1 rW r/mW */
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#if 1 /* FIXME doesn't work at the moment */
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{ "adc", 0x13, OP1F, OP_RMW_RW_R,OP_RMW_D0_R,AOT_NONE },
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{ "adc", 0x13, OP1F, OP_RMW_RW_R,OP_RMW_D8_R,AOT_NONE },
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{ "adc", 0x13, OP1F, OP_RMW_RW_R,OP_RMW_DW_R,AOT_NONE },
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{ "adc", 0x13, OP1F, OP_RMW_RW_R,OP_RMW_RW_R,AOT_NONE },
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#endif
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/* ADC 0x80 /2 ib 1 r/m8 imm8 */
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{ "adcb", 0x80, OP1F, OP_RM8_D0+2,OP_S8, AOT_NONE },
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{ "adcb", 0x80, OP1F, OP_RM8_D8+2,OP_S8, AOT_NONE },
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{ "adcb", 0x80, OP1F, OP_RM8_DW+2,OP_S8, AOT_NONE },
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{ "adc", 0x80, OP1F, OP_RM8_R8+2,OP_S8, AOT_NONE },
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/* ADC 0x81 /2 iW 1 r/mW immW */
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{ "adc", 0x81, OP1F, OP_RMW_D0+2,OP_SW, AOT_NONE },
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{ "adc", 0x81, OP1F, OP_RMW_D8+2,OP_SW, AOT_NONE },
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{ "adc", 0x81, OP1F, OP_RMW_DW+2,OP_SW, AOT_NONE },
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{ "adc", 0x81, OP1F, OP_RMW_RW+2,OP_SW, AOT_NONE },
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/* ADC 0x83 /2 ib 1 r/mW imm8 */
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{ "adcb", 0x83, OP1F, OP_RMW_D0+2,OP_S8, AOT_NONE },
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{ "adcb", 0x83, OP1F, OP_RMW_D8+2,OP_S8, AOT_NONE },
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{ "adcb", 0x83, OP1F, OP_RMW_DW+2,OP_S8, AOT_NONE },
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{ "adc", 0x83, OP1F, OP_RMW_RW+2,OP_S8, AOT_NONE },
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/* ADD 0x04 ib 1 al imm8 */
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{ "add", 0x04, OP1F, OP_al, OP_S8, AOT_NONE },
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/* ADD 0x05 iW 1 AX immW */
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{ "add", 0x05, OP1F, OP_AX, OP_SW, AOT_NONE },
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/* ADD 0x00 /r 1 r/m8 r8 */
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{ "add", 0x00, OP1F, OP_RM8_D0, OP_R8_R, AOT_NONE },
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{ "add", 0x00, OP1F, OP_RM8_D8, OP_R8_R, AOT_NONE },
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{ "add", 0x00, OP1F, OP_RM8_DW, OP_R8_R, AOT_NONE },
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{ "add", 0x00, OP1F, OP_RM8_R8, OP_R8_R, AOT_NONE },
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/* ADD 0x01 /r 1 r/mW rW */
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{ "add", 0x01, OP1F, OP_RMW_D0, OP_RW_R, AOT_NONE },
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{ "add", 0x01, OP1F, OP_RMW_D8, OP_RW_R, AOT_NONE },
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{ "add", 0x01, OP1F, OP_RMW_DW, OP_RW_R, AOT_NONE },
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{ "add", 0x01, OP1F, OP_RMW_RW, OP_RW_R, AOT_NONE },
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/* ADD 0x02 /r 1 r8 r/m8 */
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#if 1 /* FIXME probably doesn't work at the moment */
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{ "add", 0x02, OP1F, OP_R8_R, OP_RM8_D0_R,AOT_NONE },
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{ "add", 0x02, OP1F, OP_R8_R, OP_RM8_D8_R,AOT_NONE },
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{ "add", 0x02, OP1F, OP_R8_R, OP_RM8_DW_R,AOT_NONE },
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{ "add", 0x02, OP1F, OP_R8_R, OP_RM8_R8_R,AOT_NONE },
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#endif
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/* ADD 0x03 /r 1 rW r/mW */
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#if 1 /* FIXME probably doesn't work at the moment */
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{ "add", 0x03, OP1F, OP_RMW_RW_R,OP_RMW_D0_R,AOT_NONE },
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{ "add", 0x03, OP1F, OP_RMW_RW_R,OP_RMW_D8_R,AOT_NONE },
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{ "add", 0x03, OP1F, OP_RMW_RW_R,OP_RMW_DW_R,AOT_NONE },
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{ "add", 0x03, OP1F, OP_RMW_RW_R,OP_RMW_RW_R,AOT_NONE },
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#endif
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/* ADD 0x80 /0 ib 1 r/m8 imm8 */
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{ "addb", 0x80, OP1F, OP_RM8_D0+0,OP_S8, AOT_NONE },
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{ "addb", 0x80, OP1F, OP_RM8_D8+0,OP_S8, AOT_NONE },
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{ "addb", 0x80, OP1F, OP_RM8_DW+0,OP_S8, AOT_NONE },
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{ "add", 0x80, OP1F, OP_RM8_R8+0,OP_S8, AOT_NONE },
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/* ADD 0x81 /0 iW 1 r/mW immW */
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{ "add", 0x81, OP1F, OP_RMW_D0+0,OP_SW, AOT_NONE },
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{ "add", 0x81, OP1F, OP_RMW_D8+0,OP_SW, AOT_NONE },
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{ "add", 0x81, OP1F, OP_RMW_DW+0,OP_SW, AOT_NONE },
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{ "add", 0x81, OP1F, OP_RMW_RW+0,OP_SW, AOT_NONE },
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/* ADD 0x83 /0 ib 1 r/mW imm8 */
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{ "addb", 0x83, OP1F, OP_RMW_D0+0,OP_S8, AOT_NONE },
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{ "addb", 0x83, OP1F, OP_RMW_D8+0,OP_S8, AOT_NONE },
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{ "addb", 0x83, OP1F, OP_RMW_DW+0,OP_S8, AOT_NONE },
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{ "add", 0x83, OP1F, OP_RMW_RW+0,OP_S8, AOT_NONE },
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/* AND 0x24 ib 1 al imm8 */
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{ "and", 0x24, OP1F, OP_al, OP_S8, AOT_NONE },
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/* AND 0x25 iW 1 AX immW */
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{ "and", 0x25, OP1F, OP_AX, OP_SW, AOT_NONE },
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/* AND 0x20 /r 1 r/m8 r8 */
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{ "and", 0x20, OP1F, OP_RM8_D0, OP_R8_R, AOT_NONE },
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{ "and", 0x20, OP1F, OP_RM8_D8, OP_R8_R, AOT_NONE },
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{ "and", 0x20, OP1F, OP_RM8_DW, OP_R8_R, AOT_NONE },
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{ "and", 0x20, OP1F, OP_RM8_R8, OP_R8_R, AOT_NONE },
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/* AND 0x21 /r 1 r/mW rW */
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{ "and", 0x21, OP1F, OP_RMW_D0, OP_RW_R, AOT_NONE },
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{ "and", 0x21, OP1F, OP_RMW_D8, OP_RW_R, AOT_NONE },
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{ "and", 0x21, OP1F, OP_RMW_DW, OP_RW_R, AOT_NONE },
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{ "and", 0x21, OP1F, OP_RMW_RW, OP_RW_R, AOT_NONE },
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/* AND 0x22 /r 1 r8 r/m8 */
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#if 1 /* FIXME probably doesn't work at the moment */
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{ "and", 0x22, OP1F, OP_RM8_R8_R,OP_RM8_D0_R,AOT_NONE },
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{ "and", 0x22, OP1F, OP_RM8_R8_R,OP_RM8_D8_R,AOT_NONE },
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{ "and", 0x22, OP1F, OP_RM8_R8_R,OP_RM8_DW_R,AOT_NONE },
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{ "and", 0x22, OP1F, OP_RM8_R8_R,OP_RM8_R8_R,AOT_NONE },
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#endif
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/* AND 0x23 /r 1 rW r/mW */
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#if 1 /* FIXME probably doesn't work at the moment */
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{ "and", 0x23, OP1F, OP_RMW_RW_R,OP_RMW_D0_R,AOT_NONE },
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{ "and", 0x23, OP1F, OP_RMW_RW_R,OP_RMW_D8_R,AOT_NONE },
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{ "and", 0x23, OP1F, OP_RMW_RW_R,OP_RMW_DW_R,AOT_NONE },
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{ "and", 0x23, OP1F, OP_RMW_RW_R,OP_RMW_RW_R,AOT_NONE },
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#endif
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/* AND 0x80 /0 ib 1 r/m8 imm8 */
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{ "andb", 0x80, OP1F, OP_RM8_D0+4,OP_S8, AOT_NONE },
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{ "andb", 0x80, OP1F, OP_RM8_D8+4,OP_S8, AOT_NONE },
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{ "andb", 0x80, OP1F, OP_RM8_DW+4,OP_S8, AOT_NONE },
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{ "and", 0x80, OP1F, OP_RM8_R8+4,OP_S8, AOT_NONE },
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/* AND 0x81 /0 iW 1 r/mW immW */
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{ "and", 0x81, OP1F, OP_RMW_D0+4,OP_SW, AOT_NONE },
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{ "and", 0x81, OP1F, OP_RMW_D8+4,OP_SW, AOT_NONE },
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{ "and", 0x81, OP1F, OP_RMW_DW+4,OP_SW, AOT_NONE },
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{ "and", 0x81, OP1F, OP_RMW_RW+4,OP_SW, AOT_NONE },
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/* AND 0x83 /0 ib 1 r/mW imm8 */
|
|
{ "andb", 0x83, OP1F, OP_RMW_D0+4,OP_S8, AOT_NONE },
|
|
{ "andb", 0x83, OP1F, OP_RMW_D8+4,OP_S8, AOT_NONE },
|
|
{ "andb", 0x83, OP1F, OP_RMW_DW+4,OP_S8, AOT_NONE },
|
|
{ "and", 0x83, OP1F, OP_RMW_RW+4,OP_S8, AOT_NONE },
|
|
/* ARPL */
|
|
/* FIXME implement */
|
|
/* BOUND */
|
|
/* FIXME implement */
|
|
/* BSF 0x0fbc 2 rW r/mW */
|
|
#if 1 /* FIXME doesn't work at the moment */
|
|
{ "bsf", 0x0fbc, OP2F, OP_RMW_RW_R,OP_RMW_D0_R,AOT_NONE },
|
|
{ "bsf", 0x0fbc, OP2F, OP_RMW_RW_R,OP_RMW_D8_R,AOT_NONE },
|
|
{ "bsf", 0x0fbc, OP2F, OP_RMW_RW_R,OP_RMW_DW_R,AOT_NONE },
|
|
{ "bsf", 0x0fbc, OP2F, OP_RMW_RW_R,OP_RMW_RW_R,AOT_NONE },
|
|
#endif
|
|
/* BSR 0x0fbd 2 rW r/mW */
|
|
#if 1 /* FIXME doesn't work at the moment */
|
|
{ "bsr", 0x0fbd, OP2F, OP_RMW_RW_R,OP_RMW_D0_R,AOT_NONE },
|
|
{ "bsr", 0x0fbd, OP2F, OP_RMW_RW_R,OP_RMW_D8_R,AOT_NONE },
|
|
{ "bsr", 0x0fbd, OP2F, OP_RMW_RW_R,OP_RMW_DW_R,AOT_NONE },
|
|
{ "bsr", 0x0fbd, OP2F, OP_RMW_RW_R,OP_RMW_RW_R,AOT_NONE },
|
|
#endif
|
|
/* BT 0x0fa3 2 r/mW rW */
|
|
{ "bt", 0x0fa3, OP2F, OP_RMW_D0, OP_RW_R, AOT_NONE },
|
|
{ "bt", 0x0fa3, OP2F, OP_RMW_D8, OP_RW_R, AOT_NONE },
|
|
{ "bt", 0x0fa3, OP2F, OP_RMW_DW, OP_RW_R, AOT_NONE },
|
|
{ "bt", 0x0fa3, OP2F, OP_RMW_RW, OP_RW_R, AOT_NONE },
|
|
/* BT 0x0fba /4 ib 2 r/mW imm8 */
|
|
{ "bt", 0x0fba, OP2F, OP_RMW_D0+4,OP_S8, AOT_NONE },
|
|
{ "bt", 0x0fba, OP2F, OP_RMW_D8+4,OP_S8, AOT_NONE },
|
|
{ "bt", 0x0fba, OP2F, OP_RMW_DW+4,OP_S8, AOT_NONE },
|
|
{ "bt", 0x0fba, OP2F, OP_RMW_RW+4,OP_S8, AOT_NONE },
|
|
/* BTC 0x0fbb 2 r/mW rW */
|
|
{ "btc", 0x0fbb, OP2F, OP_RMW_D0, OP_RW_R, AOT_NONE },
|
|
{ "btc", 0x0fbb, OP2F, OP_RMW_D8, OP_RW_R, AOT_NONE },
|
|
{ "btc", 0x0fbb, OP2F, OP_RMW_DW, OP_RW_R, AOT_NONE },
|
|
{ "btc", 0x0fbb, OP2F, OP_RMW_RW, OP_RW_R, AOT_NONE },
|
|
/* BTC 0x0fba /7 ib 2 r/mW imm8 */
|
|
{ "btc", 0x0fba, OP2F, OP_RMW_D0+7,OP_S8, AOT_NONE },
|
|
{ "btc", 0x0fba, OP2F, OP_RMW_D8+7,OP_S8, AOT_NONE },
|
|
{ "btc", 0x0fba, OP2F, OP_RMW_DW+7,OP_S8, AOT_NONE },
|
|
{ "btc", 0x0fba, OP2F, OP_RMW_RW+7,OP_S8, AOT_NONE },
|
|
/* BTR 0x0fb3 2 r/mW rW */
|
|
{ "btr", 0x0fb3, OP2F, OP_RMW_D0, OP_RW_R, AOT_NONE },
|
|
{ "btr", 0x0fb3, OP2F, OP_RMW_D8, OP_RW_R, AOT_NONE },
|
|
{ "btr", 0x0fb3, OP2F, OP_RMW_DW, OP_RW_R, AOT_NONE },
|
|
{ "btr", 0x0fb3, OP2F, OP_RMW_RW, OP_RW_R, AOT_NONE },
|
|
/* BTR 0x0fba /6 ib 2 r/mW imm8 */
|
|
{ "btr", 0x0fba, OP2F, OP_RMW_D0+6,OP_S8, AOT_NONE },
|
|
{ "btr", 0x0fba, OP2F, OP_RMW_D8+6,OP_S8, AOT_NONE },
|
|
{ "btr", 0x0fba, OP2F, OP_RMW_DW+6,OP_S8, AOT_NONE },
|
|
{ "btr", 0x0fba, OP2F, OP_RMW_RW+6,OP_S8, AOT_NONE },
|
|
/* BTS 0x0fab 2 r/mW rW */
|
|
{ "bts", 0x0fab, OP2F, OP_RMW_D0, OP_RW_R, AOT_NONE },
|
|
{ "bts", 0x0fab, OP2F, OP_RMW_D8, OP_RW_R, AOT_NONE },
|
|
{ "bts", 0x0fab, OP2F, OP_RMW_DW, OP_RW_R, AOT_NONE },
|
|
{ "bts", 0x0fab, OP2F, OP_RMW_RW, OP_RW_R, AOT_NONE },
|
|
/* BTS 0x0fba /5 ib 2 r/mW imm8 */
|
|
{ "bts", 0x0fba, OP2F, OP_RMW_D0+5,OP_S8, AOT_NONE },
|
|
{ "bts", 0x0fba, OP2F, OP_RMW_D8+5,OP_S8, AOT_NONE },
|
|
{ "bts", 0x0fba, OP2F, OP_RMW_DW+5,OP_S8, AOT_NONE },
|
|
{ "bts", 0x0fba, OP2F, OP_RMW_RW+5,OP_S8, AOT_NONE },
|
|
/* CALL */
|
|
{ "call", 0xe8, OP1F, OP_SW, AOT_NONE, AOT_NONE },
|
|
/* FIXME implement */
|
|
#if defined(ARCH_i386_real)
|
|
/* CBW 0x98 1 */
|
|
{ "cbw", 0x98, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
#else
|
|
/* CWDE 0x98 1 */
|
|
{ "cwde", 0x98, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
#endif
|
|
/* CLC 0xf8 1 */
|
|
{ "clc", 0xf8, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* CLD 0xfc 1 */
|
|
{ "cld", 0xfc, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* CLI 0xfa 1 */
|
|
{ "cli", 0xfa, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* CLTS 0xfa 2 */
|
|
{ "clts", 0x0f06, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* CMC 0xf5 1 */
|
|
{ "cmc", 0xf5, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* CMOVcc */
|
|
/* FIXME implement */
|
|
/* CMP */
|
|
/* FIXME implement */
|
|
#if defined(ARCH_i386_real)
|
|
/* CWD 0x99 1 */
|
|
{ "cwd", 0x99, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
#else
|
|
/* CDQ 0x99 1 */
|
|
{ "cdq", 0x99, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
#endif
|
|
#ifndef ARCH_amd64
|
|
/* DAA 0x27 1 */
|
|
{ "daa", 0x27, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
#endif
|
|
#ifndef ARCH_amd64
|
|
/* DAS 0x2f 1 */
|
|
{ "das", 0x2f, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
#endif
|
|
#ifndef ARCH_amd64
|
|
/* DEC 0x48 +rd 1 */
|
|
{ "dec", 0x48, OP1F, OP_AX, AOT_NONE, AOT_NONE },
|
|
{ "dec", 0x49, OP1F, OP_CX, AOT_NONE, AOT_NONE },
|
|
{ "dec", 0x4a, OP1F, OP_DX, AOT_NONE, AOT_NONE },
|
|
{ "dec", 0x4b, OP1F, OP_BX, AOT_NONE, AOT_NONE },
|
|
{ "dec", 0x4c, OP1F, OP_SP, AOT_NONE, AOT_NONE },
|
|
{ "dec", 0x4d, OP1F, OP_BP, AOT_NONE, AOT_NONE },
|
|
{ "dec", 0x4e, OP1F, OP_SI, AOT_NONE, AOT_NONE },
|
|
{ "dec", 0x4f, OP1F, OP_DI, AOT_NONE, AOT_NONE },
|
|
#endif
|
|
/* DEC 0xfe /1 1 r/m8 */
|
|
{ "decb", 0xfe, OP1F, OP_RM8_D0+1,AOT_NONE, AOT_NONE },
|
|
{ "decb", 0xfe, OP1F, OP_RM8_D8+1,AOT_NONE, AOT_NONE },
|
|
{ "decb", 0xfe, OP1F, OP_RM8_DW+1,AOT_NONE, AOT_NONE },
|
|
{ "dec", 0xfe, OP1F, OP_RM8_R8+1,AOT_NONE, AOT_NONE },
|
|
/* DEC 0xff /1 1 r/mW */
|
|
{ "dec", 0xff, OP1F, OP_RMW_D0+1,AOT_NONE, AOT_NONE },
|
|
{ "dec", 0xff, OP1F, OP_RMW_D8+1,AOT_NONE, AOT_NONE },
|
|
{ "dec", 0xff, OP1F, OP_RMW_DW+1,AOT_NONE, AOT_NONE },
|
|
{ "dec", 0xff, OP1F, OP_RMW_RW+1,AOT_NONE, AOT_NONE },
|
|
/* DIV 0xf6 /6 1 r/m8 */
|
|
{ "divb", 0xf6, OP1F, OP_RM8_D0+6,AOT_NONE, AOT_NONE },
|
|
{ "divb", 0xf6, OP1F, OP_RM8_D8+6,AOT_NONE, AOT_NONE },
|
|
{ "divb", 0xf6, OP1F, OP_RM8_DW+6,AOT_NONE, AOT_NONE },
|
|
{ "div", 0xf6, OP1F, OP_RM8_R8+6,AOT_NONE, AOT_NONE },
|
|
/* DIV 0xf7 /6 1 r/mW */
|
|
{ "div", 0xf7, OP1F, OP_RMW_D0+6,AOT_NONE, AOT_NONE },
|
|
{ "div", 0xf7, OP1F, OP_RMW_D8+6,AOT_NONE, AOT_NONE },
|
|
{ "div", 0xf7, OP1F, OP_RMW_DW+6,AOT_NONE, AOT_NONE },
|
|
{ "div", 0xf7, OP1F, OP_RMW_RW+6,AOT_NONE, AOT_NONE },
|
|
/* ENTER 0xc8 iw 1 imm16 imm8 */
|
|
{ "enter", 0xc8, OP1F, OP_U16, OP_U8, AOT_NONE },
|
|
/* F2XM1 0xd9f0 2 */
|
|
{ "f2xm1", 0xd9f0, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* FABS 0xd9e1 2 */
|
|
{ "fabs", 0xd9e1, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* FADD 0xd8 /0 1 m32real */
|
|
/* FIXME implement */
|
|
/* FADD 0xdc /0 1 m64real */
|
|
/* FIXME implement */
|
|
/* FADD 0xd8c0 +i 2 st(0) st(i) */
|
|
{ "fadd", 0xd8c0, OP2F, OP_st0, OP_st0, AOT_NONE },
|
|
{ "fadd", 0xd8c1, OP2F, OP_st0, OP_st1, AOT_NONE },
|
|
{ "fadd", 0xd8c2, OP2F, OP_st0, OP_st2, AOT_NONE },
|
|
{ "fadd", 0xd8c3, OP2F, OP_st0, OP_st3, AOT_NONE },
|
|
{ "fadd", 0xd8c4, OP2F, OP_st0, OP_st4, AOT_NONE },
|
|
{ "fadd", 0xd8c5, OP2F, OP_st0, OP_st5, AOT_NONE },
|
|
{ "fadd", 0xd8c6, OP2F, OP_st0, OP_st6, AOT_NONE },
|
|
{ "fadd", 0xd8c7, OP2F, OP_st0, OP_st7, AOT_NONE },
|
|
/* FADD 0xdcc0 +i 2 st(i) st(0) */
|
|
{ "fadd", 0xdcc0, OP2F, OP_st0, OP_st0, AOT_NONE },
|
|
{ "fadd", 0xdcc1, OP2F, OP_st1, OP_st0, AOT_NONE },
|
|
{ "fadd", 0xdcc2, OP2F, OP_st2, OP_st0, AOT_NONE },
|
|
{ "fadd", 0xdcc3, OP2F, OP_st3, OP_st0, AOT_NONE },
|
|
{ "fadd", 0xdcc4, OP2F, OP_st4, OP_st0, AOT_NONE },
|
|
{ "fadd", 0xdcc5, OP2F, OP_st5, OP_st0, AOT_NONE },
|
|
{ "fadd", 0xdcc6, OP2F, OP_st6, OP_st0, AOT_NONE },
|
|
{ "fadd", 0xdcc7, OP2F, OP_st7, OP_st0, AOT_NONE },
|
|
/* FADDP 0xdec1 2 */
|
|
{ "faddp", 0xdec1, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* FADDP 0xdec0 +i 2 st(i) st(0) */
|
|
{ "faddp", 0xdec0, OP2F, OP_st0, OP_st0, AOT_NONE },
|
|
{ "faddp", 0xdec1, OP2F, OP_st1, OP_st0, AOT_NONE },
|
|
{ "faddp", 0xdec2, OP2F, OP_st2, OP_st0, AOT_NONE },
|
|
{ "faddp", 0xdec3, OP2F, OP_st3, OP_st0, AOT_NONE },
|
|
{ "faddp", 0xdec4, OP2F, OP_st4, OP_st0, AOT_NONE },
|
|
{ "faddp", 0xdec5, OP2F, OP_st5, OP_st0, AOT_NONE },
|
|
{ "faddp", 0xdec6, OP2F, OP_st6, OP_st0, AOT_NONE },
|
|
{ "faddp", 0xdec7, OP2F, OP_st7, OP_st0, AOT_NONE },
|
|
/* FBLD 0xdf /4 1 m80dec */
|
|
/* FIXME implement */
|
|
/* FBSTP 0xdf /6 1 m80bcd */
|
|
/* FIXME implement */
|
|
/* FCHS 0xd9e0 2 */
|
|
{ "fchs", 0xd9e0, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* FCLEX 0x9bdbe2 3 */
|
|
{ "fclex", 0x9bdbe2, OP3F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* FCMOVcc */
|
|
/* FIXME implement */
|
|
/* FCOM */
|
|
/* FIXME implement */
|
|
/* FCOM 0xd8d1 2 */
|
|
{ "fcom", 0xd8d1, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* FCOM 0xd8d0 +i 2 st(i) */
|
|
{ "fcom", 0xd8d0, OP2F, OP_st0, AOT_NONE, AOT_NONE },
|
|
{ "fcom", 0xd8d1, OP2F, OP_st1, AOT_NONE, AOT_NONE },
|
|
{ "fcom", 0xd8d2, OP2F, OP_st2, AOT_NONE, AOT_NONE },
|
|
{ "fcom", 0xd8d3, OP2F, OP_st3, AOT_NONE, AOT_NONE },
|
|
{ "fcom", 0xd8d4, OP2F, OP_st4, AOT_NONE, AOT_NONE },
|
|
{ "fcom", 0xd8d5, OP2F, OP_st5, AOT_NONE, AOT_NONE },
|
|
{ "fcom", 0xd8d6, OP2F, OP_st6, AOT_NONE, AOT_NONE },
|
|
{ "fcom", 0xd8d7, OP2F, OP_st7, AOT_NONE, AOT_NONE },
|
|
/* FCOMP 0xd8d9 2 */
|
|
{ "fcomp", 0xd8d9, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* FCOMP 0xd8d8 +i 2 st(i) */
|
|
{ "fcomp", 0xd8d8, OP2F, OP_st0, AOT_NONE, AOT_NONE },
|
|
{ "fcomp", 0xd8d9, OP2F, OP_st1, AOT_NONE, AOT_NONE },
|
|
{ "fcomp", 0xd8da, OP2F, OP_st2, AOT_NONE, AOT_NONE },
|
|
{ "fcomp", 0xd8db, OP2F, OP_st3, AOT_NONE, AOT_NONE },
|
|
{ "fcomp", 0xd8dc, OP2F, OP_st4, AOT_NONE, AOT_NONE },
|
|
{ "fcomp", 0xd8dd, OP2F, OP_st5, AOT_NONE, AOT_NONE },
|
|
{ "fcomp", 0xd8de, OP2F, OP_st6, AOT_NONE, AOT_NONE },
|
|
{ "fcomp", 0xd8df, OP2F, OP_st7, AOT_NONE, AOT_NONE },
|
|
/* FCOMPP 0xded9 2 */
|
|
{ "fcompp", 0xded9, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* FCOS 0xd9ff 2 */
|
|
{ "fcos", 0xd9ff, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* FDECSTP 0xd9f6 2 */
|
|
{ "fdecstp", 0xd9f6, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* FDIV 0xd8 /6 1 m32real */
|
|
/* FIXME implement */
|
|
/* FDIV 0xdc /6 1 m64real */
|
|
/* FIXME implement */
|
|
/* FDIV 0xd8f0 +i 2 st(0) st(i) */
|
|
{ "fdiv", 0xd8f0, OP2F, OP_st0, OP_st0, AOT_NONE },
|
|
{ "fdiv", 0xd8f1, OP2F, OP_st0, OP_st1, AOT_NONE },
|
|
{ "fdiv", 0xd8f2, OP2F, OP_st0, OP_st2, AOT_NONE },
|
|
{ "fdiv", 0xd8f3, OP2F, OP_st0, OP_st3, AOT_NONE },
|
|
{ "fdiv", 0xd8f4, OP2F, OP_st0, OP_st4, AOT_NONE },
|
|
{ "fdiv", 0xd8f5, OP2F, OP_st0, OP_st5, AOT_NONE },
|
|
{ "fdiv", 0xd8f6, OP2F, OP_st0, OP_st6, AOT_NONE },
|
|
{ "fdiv", 0xd8f7, OP2F, OP_st0, OP_st7, AOT_NONE },
|
|
/* FDIV 0xdcf8 +i 2 st(0) st(i) */
|
|
{ "fdiv", 0xdcf8, OP2F, OP_st0, OP_st0, AOT_NONE },
|
|
{ "fdiv", 0xdcf9, OP2F, OP_st1, OP_st0, AOT_NONE },
|
|
{ "fdiv", 0xdcfa, OP2F, OP_st2, OP_st0, AOT_NONE },
|
|
{ "fdiv", 0xdcfb, OP2F, OP_st3, OP_st0, AOT_NONE },
|
|
{ "fdiv", 0xdcfc, OP2F, OP_st4, OP_st0, AOT_NONE },
|
|
{ "fdiv", 0xdcfd, OP2F, OP_st5, OP_st0, AOT_NONE },
|
|
{ "fdiv", 0xdcfe, OP2F, OP_st6, OP_st0, AOT_NONE },
|
|
{ "fdiv", 0xdcff, OP2F, OP_st7, OP_st0, AOT_NONE },
|
|
/* FDIVP 0xdef9 2 */
|
|
{ "fdivp", 0xdef9, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* FDIVP 0xdef8 +i 2 st(0) st(i) */
|
|
{ "fdivp", 0xdef8, OP2F, OP_st0, OP_st0, AOT_NONE },
|
|
{ "fdivp", 0xdef9, OP2F, OP_st1, OP_st0, AOT_NONE },
|
|
{ "fdivp", 0xdefa, OP2F, OP_st2, OP_st0, AOT_NONE },
|
|
{ "fdivp", 0xdefb, OP2F, OP_st3, OP_st0, AOT_NONE },
|
|
{ "fdivp", 0xdefc, OP2F, OP_st4, OP_st0, AOT_NONE },
|
|
{ "fdivp", 0xdefd, OP2F, OP_st5, OP_st0, AOT_NONE },
|
|
{ "fdivp", 0xdefe, OP2F, OP_st6, OP_st0, AOT_NONE },
|
|
{ "fdivp", 0xdeff, OP2F, OP_st7, OP_st0, AOT_NONE },
|
|
/* FDIVR 0xd8 /7 1 m32real */
|
|
/* FIXME implement */
|
|
/* FDIVR 0xdc /7 1 m64real */
|
|
/* FIXME implement */
|
|
/* FDIVR 0xd8f8 +i 2 st(0) st(i) */
|
|
{ "fdivr", 0xd8f8, OP2F, OP_st0, OP_st0, AOT_NONE },
|
|
{ "fdivr", 0xd8f9, OP2F, OP_st0, OP_st1, AOT_NONE },
|
|
{ "fdivr", 0xd8fa, OP2F, OP_st0, OP_st2, AOT_NONE },
|
|
{ "fdivr", 0xd8fb, OP2F, OP_st0, OP_st3, AOT_NONE },
|
|
{ "fdivr", 0xd8fc, OP2F, OP_st0, OP_st4, AOT_NONE },
|
|
{ "fdivr", 0xd8fd, OP2F, OP_st0, OP_st5, AOT_NONE },
|
|
{ "fdivr", 0xd8fe, OP2F, OP_st0, OP_st6, AOT_NONE },
|
|
{ "fdivr", 0xd8ff, OP2F, OP_st0, OP_st7, AOT_NONE },
|
|
/* FDIVR 0xdcf0 +i 2 st(0) st(i) */
|
|
{ "fdivr", 0xdcf0, OP2F, OP_st0, OP_st0, AOT_NONE },
|
|
{ "fdivr", 0xdcf1, OP2F, OP_st1, OP_st0, AOT_NONE },
|
|
{ "fdivr", 0xdcf2, OP2F, OP_st2, OP_st0, AOT_NONE },
|
|
{ "fdivr", 0xdcf3, OP2F, OP_st3, OP_st0, AOT_NONE },
|
|
{ "fdivr", 0xdcf4, OP2F, OP_st4, OP_st0, AOT_NONE },
|
|
{ "fdivr", 0xdcf5, OP2F, OP_st5, OP_st0, AOT_NONE },
|
|
{ "fdivr", 0xdcf6, OP2F, OP_st6, OP_st0, AOT_NONE },
|
|
{ "fdivr", 0xdcf7, OP2F, OP_st7, OP_st0, AOT_NONE },
|
|
/* FDIVRP 0xdef1 2 */
|
|
{ "fdivrp", 0xdef1, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* FDIVRP 0xdef0 +i 2 st(0) st(i) */
|
|
{ "fdivrp", 0xdef0, OP2F, OP_st0, OP_st0, AOT_NONE },
|
|
{ "fdivrp", 0xdef1, OP2F, OP_st1, OP_st0, AOT_NONE },
|
|
{ "fdivrp", 0xdef2, OP2F, OP_st2, OP_st0, AOT_NONE },
|
|
{ "fdivrp", 0xdef3, OP2F, OP_st3, OP_st0, AOT_NONE },
|
|
{ "fdivrp", 0xdef4, OP2F, OP_st4, OP_st0, AOT_NONE },
|
|
{ "fdivrp", 0xdef5, OP2F, OP_st5, OP_st0, AOT_NONE },
|
|
{ "fdivrp", 0xdef6, OP2F, OP_st6, OP_st0, AOT_NONE },
|
|
{ "fdivrp", 0xdef7, OP2F, OP_st7, OP_st0, AOT_NONE },
|
|
/* FFREE 0xddc0 +i 2 st(i) */
|
|
{ "ffree", 0xddc0, OP2F, OP_st0, AOT_NONE, AOT_NONE },
|
|
{ "ffree", 0xddc1, OP2F, OP_st1, AOT_NONE, AOT_NONE },
|
|
{ "ffree", 0xddc2, OP2F, OP_st2, AOT_NONE, AOT_NONE },
|
|
{ "ffree", 0xddc3, OP2F, OP_st3, AOT_NONE, AOT_NONE },
|
|
{ "ffree", 0xddc4, OP2F, OP_st4, AOT_NONE, AOT_NONE },
|
|
{ "ffree", 0xddc5, OP2F, OP_st5, AOT_NONE, AOT_NONE },
|
|
{ "ffree", 0xddc6, OP2F, OP_st6, AOT_NONE, AOT_NONE },
|
|
{ "ffree", 0xddc7, OP2F, OP_st7, AOT_NONE, AOT_NONE },
|
|
/* FIADD 0xda /0 1 m32int */
|
|
/* FIXME implement */
|
|
/* FIADD 0xde /0 1 m64int */
|
|
/* FIXME implement */
|
|
/* FIDIVR 0xda /7 1 m32int */
|
|
/* FIXME implement */
|
|
/* FIDIVR 0xde /7 1 m64int */
|
|
/* FIXME implement */
|
|
/* FILD 0xdf /0 1 m16int */
|
|
/* FIXME implement */
|
|
/* FILD 0xdb /0 1 m32int */
|
|
/* FIXME implement */
|
|
/* FILD 0xdf /5 1 m64int */
|
|
/* FIXME implement */
|
|
/* FINCSTP 0xd9f7 2 */
|
|
{ "fincstp", 0xd9f7, OP3F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* FINIT 0x9bdbe3 3 */
|
|
{ "finit", 0x9bdbe3, OP3F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* FIST 0xdf /2 1 m16int */
|
|
/* FIXME implement */
|
|
/* FIST 0xdb /2 1 m32int */
|
|
/* FIXME implement */
|
|
/* FISTP 0xdf /3 1 m16int */
|
|
/* FIXME implement */
|
|
/* FISTP 0xdb /3 1 m32int */
|
|
/* FIXME implement */
|
|
/* FISTP 0xdf /7 1 m64int */
|
|
/* FIXME implement */
|
|
/* FLD 0xd9 /0 1 m32real */
|
|
/* FIXME implement */
|
|
/* FLD 0xdd /0 1 m64real */
|
|
/* FIXME implement */
|
|
/* FLD 0xdb /5 1 m80real */
|
|
/* FIXME implement */
|
|
/* FLD 0xd9c0 +i 2 st(i) */
|
|
{ "fld", 0xd9c0, OP2F, OP_st0, AOT_NONE, AOT_NONE },
|
|
{ "fld", 0xd9c1, OP2F, OP_st1, AOT_NONE, AOT_NONE },
|
|
{ "fld", 0xd9c2, OP2F, OP_st2, AOT_NONE, AOT_NONE },
|
|
{ "fld", 0xd9c3, OP2F, OP_st3, AOT_NONE, AOT_NONE },
|
|
{ "fld", 0xd9c4, OP2F, OP_st4, AOT_NONE, AOT_NONE },
|
|
{ "fld", 0xd9c5, OP2F, OP_st5, AOT_NONE, AOT_NONE },
|
|
{ "fld", 0xd9c6, OP2F, OP_st6, AOT_NONE, AOT_NONE },
|
|
{ "fld", 0xd9c7, OP2F, OP_st7, AOT_NONE, AOT_NONE },
|
|
/* FLD1 0xd9e8 2 */
|
|
{ "fld1", 0xd9e8, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* FLDL2E 0xd9ea 2 */
|
|
{ "fld2e", 0xd9ea, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* FLDL2T 0xd9e9 2 */
|
|
{ "fld2t", 0xd9e9, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* FLDLG2 0xd9ec 2 */
|
|
{ "fldg2", 0xd9ec, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* FLDLN2 0xd9ed 2 */
|
|
{ "fldn2", 0xd9ed, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* FLDPI 0xd9eb 2 */
|
|
{ "fldpi", 0xd9eb, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* FLDZ 0xd9ee 2 */
|
|
{ "fldz", 0xd9ee, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* FNCLEX 0xdbe2 2 */
|
|
{ "fnclex", 0xdbe2, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* FNINIT 0xdbe3 2 */
|
|
{ "fninit", 0xdbe3, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* FNOP 0xd9d0 2 */
|
|
{ "fnop", 0xd9d0, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* FWAIT 0x9b 1 */
|
|
{ "fwait", 0x9b, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* FYL2XP1 0xd9f9 2 */
|
|
{ "fyl2xp1", 0xd9f9, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* HLT 0xf4 1 */
|
|
{ "hlt", 0xf4, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* IDIV */
|
|
/* FIXME implement */
|
|
/* IMUL */
|
|
/* FIXME implement */
|
|
/* IN 0xe4 1 al imm8 */
|
|
{ "in", 0xe4, OP1F, OP_al, OP_S8, AOT_NONE },
|
|
/* IN 0xe5 1 AX imm8 */
|
|
{ "in", 0xe5, OP1F, OP_AX, OP_S8, AOT_NONE },
|
|
/* IN 0xec 1 al dx */
|
|
{ "in", 0xec, OP1F, OP_al, OP_dx, AOT_NONE },
|
|
/* IN 0xed 1 AX dx */
|
|
{ "in", 0xed, OP1F, OP_AX, OP_dx, AOT_NONE },
|
|
/* INC 0x40 +rd 1 */
|
|
{ "inc", 0x40, OP1F, OP_AX, AOT_NONE, AOT_NONE },
|
|
{ "inc", 0x41, OP1F, OP_CX, AOT_NONE, AOT_NONE },
|
|
{ "inc", 0x42, OP1F, OP_DX, AOT_NONE, AOT_NONE },
|
|
{ "inc", 0x43, OP1F, OP_BX, AOT_NONE, AOT_NONE },
|
|
{ "inc", 0x44, OP1F, OP_SP, AOT_NONE, AOT_NONE },
|
|
{ "inc", 0x45, OP1F, OP_BP, AOT_NONE, AOT_NONE },
|
|
{ "inc", 0x46, OP1F, OP_SI, AOT_NONE, AOT_NONE },
|
|
{ "inc", 0x47, OP1F, OP_DI, AOT_NONE, AOT_NONE },
|
|
/* INC 0xfe /0 1 r/m8 */
|
|
{ "incb", 0xfe, OP1F, OP_RM8_D0+0,AOT_NONE, AOT_NONE },
|
|
{ "incb", 0xfe, OP1F, OP_RM8_D8+0,AOT_NONE, AOT_NONE },
|
|
{ "incb", 0xfe, OP1F, OP_RM8_DW+0,AOT_NONE, AOT_NONE },
|
|
{ "inc", 0xfe, OP1F, OP_RM8_R8+0,AOT_NONE, AOT_NONE },
|
|
/* INC 0xff /0 1 r/mW */
|
|
{ "inc", 0xff, OP1F, OP_RMW_D0+0,AOT_NONE, AOT_NONE },
|
|
{ "inc", 0xff, OP1F, OP_RMW_D8+0,AOT_NONE, AOT_NONE },
|
|
{ "inc", 0xff, OP1F, OP_RMW_DW+0,AOT_NONE, AOT_NONE },
|
|
{ "inc", 0xff, OP1F, OP_RMW_RW+0,AOT_NONE, AOT_NONE },
|
|
/* INSB 0x6c 1 */
|
|
{ "insb", 0x6c, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
#ifdef ARCH_i386_real
|
|
/* INSW 0x6d 1 */
|
|
{ "insw", 0x6d, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
#else
|
|
/* INSD 0x6d 1 */
|
|
{ "insd", 0x6d, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
#endif
|
|
/* INT 0xcd 1 imm8 */
|
|
{ "int", 0xcd, OP1F, OP_U8, AOT_NONE, AOT_NONE },
|
|
/* INT 0xcc 1 3 */
|
|
{ "int", 0xcc, OP1F, OP_C3, AOT_NONE, AOT_NONE },
|
|
/* INT3 0xcc 1 */
|
|
{ "int3", 0xcc, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* INTO 0xce 1 */
|
|
{ "into", 0xce, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* INVD 0x0f08 2 */
|
|
{ "invd", 0x0f08, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* IRET 0xcf 1 */
|
|
{ "iret", 0xcf, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* IRETD 0xcf 1 */
|
|
{ "iretd", 0xcf, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* JMP 0xeb 1 imm8 */
|
|
{ "jmp", 0xeb, OP1F, OP_S8, AOT_NONE, AOT_NONE },
|
|
/* JMP 0xe9 1 immW */
|
|
{ "jmp", 0xe9, OP1F, OP_SW, AOT_NONE, AOT_NONE },
|
|
/* JMP 0xff /4 1 r/mW */
|
|
{ "jmp", 0xff, OP1F, OP_RMW_D0+4,AOT_NONE, AOT_NONE },
|
|
{ "jmp", 0xff, OP1F, OP_RMW_D8+4,AOT_NONE, AOT_NONE },
|
|
{ "jmp", 0xff, OP1F, OP_RMW_DW+4,AOT_NONE, AOT_NONE },
|
|
{ "jmp", 0xff, OP1F, OP_RMW_RW+4,AOT_NONE, AOT_NONE },
|
|
/* LAHF 0x9f 1 */
|
|
{ "lahf", 0x9f, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* LEAVE 0xc9 1 */
|
|
{ "leave", 0xc9, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* LOCK 0xf0 1 */
|
|
{ "lock", 0xf0, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* LODSB 0xac 1 */
|
|
{ "lodsb", 0xac, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
#ifdef ARCH_i386_real
|
|
/* LODSW 0xad 1 */
|
|
{ "lodsw", 0xad, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
#else
|
|
/* LODSD 0xad 1 */
|
|
{ "lodsd", 0xad, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
#endif
|
|
/* LOOP 0xe2 1 rel8 */
|
|
{ "loop", 0xe2, OP1F, OP_S8, AOT_NONE, AOT_NONE },
|
|
/* LOOPE 0xe1 1 rel8 */
|
|
{ "loope", 0xe1, OP1F, OP_S8, AOT_NONE, AOT_NONE },
|
|
/* LOOPNE 0xe0 1 rel8 */
|
|
{ "loopne", 0xe0, OP1F, OP_S8, AOT_NONE, AOT_NONE },
|
|
/* LOOPNZ 0xe0 1 rel8 */
|
|
{ "loopnz", 0xe0, OP1F, OP_S8, AOT_NONE, AOT_NONE },
|
|
/* LOOPZ 0xe1 1 rel8 */
|
|
{ "loopz", 0xe1, OP1F, OP_S8, AOT_NONE, AOT_NONE },
|
|
/* MOV 0x88 /r 1 r/m8 r8 */
|
|
{ "mov", 0x88, OP1F, OP_RM8_D0, OP_R8_R, AOT_NONE },
|
|
{ "mov", 0x88, OP1F, OP_RM8_D8, OP_R8_R, AOT_NONE },
|
|
{ "mov", 0x88, OP1F, OP_RM8_DW, OP_R8_R, AOT_NONE },
|
|
{ "mov", 0x88, OP1F, OP_RM8_R8, OP_R8_R, AOT_NONE },
|
|
/* MOV 0x89 /r 1 r/mW rW */
|
|
{ "mov", 0x89, OP1F, OP_RMW_D0, OP_RW_R, AOT_NONE },
|
|
{ "mov", 0x89, OP1F, OP_RMW_D8, OP_RW_R, AOT_NONE },
|
|
{ "mov", 0x89, OP1F, OP_RMW_DW, OP_RW_R, AOT_NONE },
|
|
{ "mov", 0x89, OP1F, OP_RMW_RW, OP_RW_R, AOT_NONE },
|
|
/* MOV 0x8a /r 1 r8 r/m8 */
|
|
{ "mov", 0x8a, OP1F, OP_R8_R, OP_RM8_D0, AOT_NONE },
|
|
{ "mov", 0x8a, OP1F, OP_R8_R, OP_RM8_D8, AOT_NONE },
|
|
{ "mov", 0x8a, OP1F, OP_R8_R, OP_RM8_DW, AOT_NONE },
|
|
{ "mov", 0x8a, OP1F, OP_R8_R, OP_RM8_R8, AOT_NONE },
|
|
/* MOV 0x8b /r 1 rW r/mW */
|
|
{ "mov", 0x8b, OP1F, OP_RW_R, OP_RMW_D0, AOT_NONE },
|
|
{ "mov", 0x8b, OP1F, OP_RW_R, OP_RMW_D8, AOT_NONE },
|
|
{ "mov", 0x8b, OP1F, OP_RW_R, OP_RMW_DW, AOT_NONE },
|
|
{ "mov", 0x8b, OP1F, OP_RW_R, OP_RMW_RW, AOT_NONE },
|
|
/* MOV 0xb0 +rb 1 r8 imm8 */
|
|
{ "mov", 0xb0, OP1F, OP_al, OP_S8, AOT_NONE },
|
|
{ "mov", 0xb1, OP1F, OP_cl, OP_S8, AOT_NONE },
|
|
{ "mov", 0xb2, OP1F, OP_dl, OP_S8, AOT_NONE },
|
|
{ "mov", 0xb3, OP1F, OP_bl, OP_S8, AOT_NONE },
|
|
{ "mov", 0xb4, OP1F, OP_ah, OP_S8, AOT_NONE },
|
|
{ "mov", 0xb5, OP1F, OP_ch, OP_S8, AOT_NONE },
|
|
{ "mov", 0xb6, OP1F, OP_dh, OP_S8, AOT_NONE },
|
|
{ "mov", 0xb7, OP1F, OP_bh, OP_S8, AOT_NONE },
|
|
/* MOV 0xb8 +rw 1 rW immW */
|
|
{ "mov", 0xb8, OP1F, OP_AX, OP_SW, AOT_NONE },
|
|
{ "mov", 0xb9, OP1F, OP_CX, OP_SW, AOT_NONE },
|
|
{ "mov", 0xba, OP1F, OP_DX, OP_SW, AOT_NONE },
|
|
{ "mov", 0xbb, OP1F, OP_BX, OP_SW, AOT_NONE },
|
|
{ "mov", 0xbc, OP1F, OP_SP, OP_SW, AOT_NONE },
|
|
{ "mov", 0xbd, OP1F, OP_BP, OP_SW, AOT_NONE },
|
|
{ "mov", 0xbe, OP1F, OP_SI, OP_SW, AOT_NONE },
|
|
{ "mov", 0xbf, OP1F, OP_DI, OP_SW, AOT_NONE },
|
|
/* MOV 0xc6 /0 1 r/m8 imm8 */
|
|
{ "mov", 0xc6, OP1F, OP_RM8_D0+0,OP_S8, AOT_NONE },
|
|
{ "mov", 0xc6, OP1F, OP_RM8_D8+0,OP_S8, AOT_NONE },
|
|
{ "mov", 0xc6, OP1F, OP_RM8_DW+0,OP_S8, AOT_NONE },
|
|
{ "mov", 0xc6, OP1F, OP_RM8_R8+0,OP_S8, AOT_NONE },
|
|
/* MOV 0xc7 /0 1 r/mW immW */
|
|
{ "mov", 0xc7, OP1F, OP_RMW_D0+0,OP_SW, AOT_NONE },
|
|
{ "mov", 0xc7, OP1F, OP_RMW_D8+0,OP_SW, AOT_NONE },
|
|
{ "mov", 0xc7, OP1F, OP_RMW_DW+0,OP_SW, AOT_NONE },
|
|
{ "mov", 0xc7, OP1F, OP_RMW_RW+0,OP_SW, AOT_NONE },
|
|
#if 1 /* FIXME doesn't work properly */
|
|
/* MOV 0x0f20 /r 2 r32 cr0-cr4 */
|
|
{ "mov", 0x0f20, OP2F, OP_RW_R, OP_cr0, AOT_NONE },
|
|
{ "mov", 0x0f20, OP2F, OP_RW_R, OP_cr2, AOT_NONE },
|
|
{ "mov", 0x0f20, OP2F, OP_RW_R, OP_cr3, AOT_NONE },
|
|
{ "mov", 0x0f20, OP2F, OP_RW_R, OP_cr4, AOT_NONE },
|
|
#endif
|
|
#if 1 /* FIXME doesn't work properly */
|
|
/* MOV 0x0f22 /r 2 cr0-cr4 r32 */
|
|
{ "mov", 0x0f22, OP2F, OP_cr0, OP_RW_R, AOT_NONE },
|
|
{ "mov", 0x0f22, OP2F, OP_cr2, OP_RW_R, AOT_NONE },
|
|
{ "mov", 0x0f22, OP2F, OP_cr3, OP_RW_R, AOT_NONE },
|
|
{ "mov", 0x0f22, OP2F, OP_cr4, OP_RW_R, AOT_NONE },
|
|
#endif
|
|
/* FIXME implement */
|
|
/* MOV 0x0f21 /r 2 r32 dr0-dr7 */
|
|
/* FIXME implement */
|
|
/* MOV 0x0f23 /r 2 dr0-dr7 r32 */
|
|
/* FIXME implement */
|
|
/* MOVSB 0xa4 1 */
|
|
{ "movsb", 0xa4, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
#ifdef ARCH_i386_real
|
|
/* MOVSW 0xa5 1 */
|
|
{ "movsw", 0xa5, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
#else
|
|
/* MOVSD 0xa5 1 */
|
|
{ "movsd", 0xa5, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
#endif
|
|
/* MOVSX 0x0fbe /r 2 rW r/m8 */
|
|
/* FIXME implement */
|
|
/* MOVSX 0x0fbf /r 2 r32 r/m16 */
|
|
/* FIXME implement */
|
|
/* MOVZX 0x0fb6 /r 2 rW r/m8 */
|
|
/* FIXME implement */
|
|
/* MOVZX 0x0fb7 /r 2 r32 r/m16 */
|
|
/* FIXME implement */
|
|
/* MUL 0xf6 /4 1 r/m8 */
|
|
{ "mulb", 0xf6, OP1F, OP_RM8_D0+4,AOT_NONE, AOT_NONE },
|
|
{ "mulb", 0xf6, OP1F, OP_RM8_D8+4,AOT_NONE, AOT_NONE },
|
|
{ "mulb", 0xf6, OP1F, OP_RM8_DW+4,AOT_NONE, AOT_NONE },
|
|
{ "mul", 0xf6, OP1F, OP_RM8_R8+4,AOT_NONE, AOT_NONE },
|
|
/* MUL 0xf7 /4 1 r/mW */
|
|
{ "mul", 0xf7, OP1F, OP_RMW_D0+4,AOT_NONE, AOT_NONE },
|
|
{ "mul", 0xf7, OP1F, OP_RMW_D8+4,AOT_NONE, AOT_NONE },
|
|
{ "mul", 0xf7, OP1F, OP_RMW_DW+4,AOT_NONE, AOT_NONE },
|
|
{ "mul", 0xf7, OP1F, OP_RMW_RW+4,AOT_NONE, AOT_NONE },
|
|
/* NEG 0xf6 /3 1 r/m8 */
|
|
{ "negb", 0xf6, OP1F, OP_RM8_D0+3,AOT_NONE, AOT_NONE },
|
|
{ "negb", 0xf6, OP1F, OP_RM8_D8+3,AOT_NONE, AOT_NONE },
|
|
{ "negb", 0xf6, OP1F, OP_RM8_DW+3,AOT_NONE, AOT_NONE },
|
|
{ "neg", 0xf6, OP1F, OP_RM8_R8+3,AOT_NONE, AOT_NONE },
|
|
/* NEG 0xf7 /3 1 r/mW */
|
|
{ "neg", 0xf7, OP1F, OP_RMW_D0+3,AOT_NONE, AOT_NONE },
|
|
{ "neg", 0xf7, OP1F, OP_RMW_D8+3,AOT_NONE, AOT_NONE },
|
|
{ "neg", 0xf7, OP1F, OP_RMW_DW+3,AOT_NONE, AOT_NONE },
|
|
{ "neg", 0xf7, OP1F, OP_RMW_RW+3,AOT_NONE, AOT_NONE },
|
|
/* NOP 0x90 1 */
|
|
{ "nop", 0x90, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* NOT 0xf6 /2 1 r/m8 */
|
|
{ "notb", 0xf6, OP1F, OP_RM8_D0+2,AOT_NONE, AOT_NONE },
|
|
{ "notb", 0xf6, OP1F, OP_RM8_D8+2,AOT_NONE, AOT_NONE },
|
|
{ "notb", 0xf6, OP1F, OP_RM8_DW+2,AOT_NONE, AOT_NONE },
|
|
{ "not", 0xf6, OP1F, OP_RM8_R8+2,AOT_NONE, AOT_NONE },
|
|
/* NOT 0xf7 /2 1 r/mW */
|
|
{ "not", 0xf7, OP1F, OP_RMW_D0+2,AOT_NONE, AOT_NONE },
|
|
{ "not", 0xf7, OP1F, OP_RMW_D8+2,AOT_NONE, AOT_NONE },
|
|
{ "not", 0xf7, OP1F, OP_RMW_DW+2,AOT_NONE, AOT_NONE },
|
|
{ "not", 0xf7, OP1F, OP_RMW_RW+2,AOT_NONE, AOT_NONE },
|
|
/* OR 0x0c ib 1 al imm8 */
|
|
{ "or", 0x0c, OP1F, OP_al, OP_S8, AOT_NONE },
|
|
/* OR 0x0d iW 1 AX immW */
|
|
{ "or", 0x0d, OP1F, OP_AX, OP_SW, AOT_NONE },
|
|
/* OR 0x80 /r 1 r/m8 r8 */
|
|
{ "or", 0x08, OP1F, OP_RM8_D0, OP_R8_R, AOT_NONE },
|
|
{ "or", 0x08, OP1F, OP_RM8_D8, OP_R8_R, AOT_NONE },
|
|
{ "or", 0x08, OP1F, OP_RM8_DW, OP_R8_R, AOT_NONE },
|
|
{ "or", 0x08, OP1F, OP_RM8_R8, OP_R8_R, AOT_NONE },
|
|
/* OR 0x09 /r 1 r/mW rW */
|
|
{ "or", 0x09, OP1F, OP_RMW_D0, OP_RW_R, AOT_NONE },
|
|
{ "or", 0x09, OP1F, OP_RMW_D8, OP_RW_R, AOT_NONE },
|
|
{ "or", 0x09, OP1F, OP_RMW_DW, OP_RW_R, AOT_NONE },
|
|
{ "or", 0x09, OP1F, OP_RMW_RW, OP_RW_R, AOT_NONE },
|
|
/* OR 0x32 /r 1 r8 r/m8 */
|
|
#if 1 /* FIXME doesn't work at the moment */
|
|
{ "or", 0x0a, OP1F, OP_RM8_R8_R,OP_RM8_D0_R,AOT_NONE },
|
|
{ "or", 0x0a, OP1F, OP_RM8_R8_R,OP_RM8_D8_R,AOT_NONE },
|
|
{ "or", 0x0a, OP1F, OP_RM8_R8_R,OP_RM8_DW_R,AOT_NONE },
|
|
{ "or", 0x0a, OP1F, OP_RM8_R8_R,OP_RM8_R8_R,AOT_NONE },
|
|
#endif
|
|
/* OR 0x0b /r 1 rW r/mW */
|
|
#if 1 /* FIXME doesn't work at the moment */
|
|
{ "or", 0x0b, OP1F, OP_RMW_RW_R,OP_RMW_D0_R,AOT_NONE },
|
|
{ "or", 0x0b, OP1F, OP_RMW_RW_R,OP_RMW_D8_R,AOT_NONE },
|
|
{ "or", 0x0b, OP1F, OP_RMW_RW_R,OP_RMW_DW_R,AOT_NONE },
|
|
{ "or", 0x0b, OP1F, OP_RMW_RW_R,OP_RMW_RW_R,AOT_NONE },
|
|
#endif
|
|
/* OR 0x80 /1 ib 1 r/m8 imm8 */
|
|
{ "orb", 0x80, OP1F, OP_RM8_D0+1,OP_S8, AOT_NONE },
|
|
{ "orb", 0x80, OP1F, OP_RM8_D8+1,OP_S8, AOT_NONE },
|
|
{ "orb", 0x80, OP1F, OP_RM8_DW+1,OP_S8, AOT_NONE },
|
|
{ "or", 0x80, OP1F, OP_RM8_R8+1,OP_S8, AOT_NONE },
|
|
/* OR 0x81 /1 iW 1 r/mW immW */
|
|
{ "or", 0x81, OP1F, OP_RMW_D0+1,OP_SW, AOT_NONE },
|
|
{ "or", 0x81, OP1F, OP_RMW_D8+1,OP_SW, AOT_NONE },
|
|
{ "or", 0x81, OP1F, OP_RMW_DW+1,OP_SW, AOT_NONE },
|
|
{ "or", 0x81, OP1F, OP_RMW_RW+1,OP_SW, AOT_NONE },
|
|
/* OR 0x83 /1 ib 1 r/mW imm8 */
|
|
{ "orb", 0x83, OP1F, OP_RMW_D0+1,OP_S8, AOT_NONE },
|
|
{ "orb", 0x83, OP1F, OP_RMW_D8+1,OP_S8, AOT_NONE },
|
|
{ "orb", 0x83, OP1F, OP_RMW_DW+1,OP_S8, AOT_NONE },
|
|
{ "or", 0x83, OP1F, OP_RMW_RW+1,OP_S8, AOT_NONE },
|
|
/* OUT 0xe6 1 imm8 al */
|
|
{ "out", 0xe6, OP1F, OP_U8, OP_al, AOT_NONE },
|
|
/* OUT 0xe7 1 imm8 AX */
|
|
{ "out", 0xe7, OP1F, OP_U8, OP_AX, AOT_NONE },
|
|
/* OUT 0xee 1 dx al */
|
|
{ "out", 0xee, OP1F, OP_dx, OP_al, AOT_NONE },
|
|
/* OUT 0xef 1 dx AX */
|
|
{ "out", 0xef, OP1F, OP_dx, OP_AX, AOT_NONE },
|
|
/* OUTSB 0x6e 1 */
|
|
{ "outsb", 0x6e, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
#ifdef ARCH_i386_real
|
|
/* OUTSW 0x6f 1 */
|
|
{ "outsw", 0x6f, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
#else
|
|
/* OUTSD 0x6f 1 */
|
|
{ "outsd", 0x6f, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
#endif
|
|
/* POP 0x07 1 es */
|
|
{ "pop", 0x07, OP1F, OP_es, AOT_NONE, AOT_NONE },
|
|
/* POP 0x17 1 ss */
|
|
{ "pop", 0x17, OP1F, OP_ss, AOT_NONE, AOT_NONE },
|
|
/* POP 0x1f 1 ds */
|
|
{ "pop", 0x1f, OP1F, OP_ds, AOT_NONE, AOT_NONE },
|
|
/* POP 0x0fa1 2 fs */
|
|
{ "pop", 0x0fa1, OP2F, OP_fs, AOT_NONE, AOT_NONE },
|
|
/* POP 0x0fa9 2 gs */
|
|
{ "pop", 0x0fa9, OP2F, OP_gs, AOT_NONE, AOT_NONE },
|
|
/* POP 0x58 +rW 1 */
|
|
{ "pop", 0x58, OP1F, OP_AX, AOT_NONE, AOT_NONE },
|
|
{ "pop", 0x59, OP1F, OP_CX, AOT_NONE, AOT_NONE },
|
|
{ "pop", 0x5a, OP1F, OP_DX, AOT_NONE, AOT_NONE },
|
|
{ "pop", 0x5b, OP1F, OP_BX, AOT_NONE, AOT_NONE },
|
|
{ "pop", 0x5c, OP1F, OP_SP, AOT_NONE, AOT_NONE },
|
|
{ "pop", 0x5d, OP1F, OP_BP, AOT_NONE, AOT_NONE },
|
|
{ "pop", 0x5e, OP1F, OP_SI, AOT_NONE, AOT_NONE },
|
|
{ "pop", 0x5f, OP1F, OP_DI, AOT_NONE, AOT_NONE },
|
|
/* POP 0x8f /0 1 rmW */
|
|
{ "pop", 0x8f, OP1F, OP_RMW_D0+0,AOT_NONE, AOT_NONE },
|
|
{ "pop", 0x8f, OP1F, OP_RMW_D8+0,AOT_NONE, AOT_NONE },
|
|
{ "pop", 0x8f, OP1F, OP_RMW_DW+0,AOT_NONE, AOT_NONE },
|
|
{ "pop", 0x8f, OP1F, OP_RMW_RW+0,AOT_NONE, AOT_NONE },
|
|
/* POPA 0x61 1 */
|
|
{ "popa", 0x61, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* POPAD 0x61 1 */
|
|
{ "popad", 0x61, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* POPF 0x9d 1 */
|
|
{ "popf", 0x9d, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* POPFD 0x9d 1 */
|
|
{ "popfd", 0x9d, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* PUSH 0x06 1 es */
|
|
{ "push", 0x06, OP1F, OP_es, AOT_NONE, AOT_NONE },
|
|
/* PUSH 0x0e 1 cs */
|
|
{ "push", 0x0e, OP1F, OP_cs, AOT_NONE, AOT_NONE },
|
|
/* PUSH 0x16 1 ss */
|
|
{ "push", 0x16, OP1F, OP_ss, AOT_NONE, AOT_NONE },
|
|
/* PUSH 0x1e 1 ds */
|
|
{ "push", 0x1e, OP1F, OP_ds, AOT_NONE, AOT_NONE },
|
|
/* PUSH 0x0fa0 2 fs */
|
|
{ "push", 0x0fa0, OP2F, OP_fs, AOT_NONE, AOT_NONE },
|
|
/* PUSH 0x0fa8 2 gs */
|
|
{ "push", 0x0fa8, OP2F, OP_gs, AOT_NONE, AOT_NONE },
|
|
/* PUSH 0x50 +rW 1 */
|
|
{ "push", 0x50, OP1F, OP_AX, AOT_NONE, AOT_NONE },
|
|
{ "push", 0x51, OP1F, OP_CX, AOT_NONE, AOT_NONE },
|
|
{ "push", 0x52, OP1F, OP_DX, AOT_NONE, AOT_NONE },
|
|
{ "push", 0x53, OP1F, OP_BX, AOT_NONE, AOT_NONE },
|
|
{ "push", 0x54, OP1F, OP_SP, AOT_NONE, AOT_NONE },
|
|
{ "push", 0x55, OP1F, OP_BP, AOT_NONE, AOT_NONE },
|
|
{ "push", 0x56, OP1F, OP_SI, AOT_NONE, AOT_NONE },
|
|
{ "push", 0x57, OP1F, OP_DI, AOT_NONE, AOT_NONE },
|
|
/* PUSH 0x6a 1 imm8 */
|
|
{ "push", 0x6a, OP1F, OP_S8, AOT_NONE, AOT_NONE },
|
|
/* PUSH 0x68 1 immW */
|
|
{ "push", 0x68, OP1F, OP_SW, AOT_NONE, AOT_NONE },
|
|
/* PUSH 0xff /6 1 rmW */
|
|
{ "push", 0xff, OP1F, OP_RMW_D0+6,AOT_NONE, AOT_NONE },
|
|
{ "push", 0xff, OP1F, OP_RMW_D8+6,AOT_NONE, AOT_NONE },
|
|
{ "push", 0xff, OP1F, OP_RMW_DW+6,AOT_NONE, AOT_NONE },
|
|
{ "push", 0xff, OP1F, OP_RMW_RW+6,AOT_NONE, AOT_NONE },
|
|
/* PUSHA 0x60 1 */
|
|
{ "pusha", 0x60, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* PUSHAD 0x60 1 */
|
|
{ "pushad", 0x60, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* PUSHF 0x9c 1 */
|
|
{ "pushf", 0x9c, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* PUSHFD 0x9c 1 */
|
|
{ "pushfd", 0x9c, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* RCL */
|
|
/* FIXME implement */
|
|
/* RCR */
|
|
/* FIXME implement */
|
|
/* ROL */
|
|
/* FIXME implement */
|
|
/* ROR */
|
|
/* FIXME implement */
|
|
/* REP */
|
|
/* FIXME implement */
|
|
/* RET 0xc2 1 imm16 */
|
|
{ "ret", 0xc2, OP1F, OP_U16, AOT_NONE, AOT_NONE },
|
|
/* RET 0xca 1 imm16 */
|
|
{ "ret", 0xca, OP1F, OP_U16, AOT_NONE, AOT_NONE },
|
|
/* RET 0xc3 1 */
|
|
{ "ret", 0xc3, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* RET 0xcb 1 */
|
|
{ "ret", 0xcb, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* RSM 0x0faa 2 */
|
|
{ "rsm", 0x0faa, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* SAHF 0x9e 1 */
|
|
{ "sahf", 0x9e, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* SAL 0xc1 /4 1 r/mW imm8 */
|
|
{ "sal", 0xc1, OP1F, OP_RMW_D0+4,OP_U8, AOT_NONE },
|
|
{ "sal", 0xc1, OP1F, OP_RMW_D8+4,OP_U8, AOT_NONE },
|
|
{ "sal", 0xc1, OP1F, OP_RMW_DW+4,OP_U8, AOT_NONE },
|
|
{ "sal", 0xc1, OP1F, OP_RMW_RW+4,OP_U8, AOT_NONE },
|
|
/* FIXME implement */
|
|
/* SAR 0xc1 /7 1 r/mW imm8 */
|
|
{ "sar", 0xc1, OP1F, OP_RMW_D0+7,OP_U8, AOT_NONE },
|
|
{ "sar", 0xc1, OP1F, OP_RMW_D8+7,OP_U8, AOT_NONE },
|
|
{ "sar", 0xc1, OP1F, OP_RMW_DW+7,OP_U8, AOT_NONE },
|
|
{ "sar", 0xc1, OP1F, OP_RMW_RW+7,OP_U8, AOT_NONE },
|
|
/* FIXME implement */
|
|
/* SHL 0xc1 /4 1 r/mW imm8 */
|
|
{ "shl", 0xc1, OP1F, OP_RMW_D0+4,OP_U8, AOT_NONE },
|
|
{ "shl", 0xc1, OP1F, OP_RMW_D8+4,OP_U8, AOT_NONE },
|
|
{ "shl", 0xc1, OP1F, OP_RMW_DW+4,OP_U8, AOT_NONE },
|
|
{ "shl", 0xc1, OP1F, OP_RMW_RW+4,OP_U8, AOT_NONE },
|
|
/* FIXME implement */
|
|
/* SHR 0xc1 /5 1 r/mW imm8 */
|
|
{ "shr", 0xc1, OP1F, OP_RMW_D0+5,OP_U8, AOT_NONE },
|
|
{ "shr", 0xc1, OP1F, OP_RMW_D8+5,OP_U8, AOT_NONE },
|
|
{ "shr", 0xc1, OP1F, OP_RMW_DW+5,OP_U8, AOT_NONE },
|
|
{ "shr", 0xc1, OP1F, OP_RMW_RW+5,OP_U8, AOT_NONE },
|
|
/* FIXME implement */
|
|
/* SBB 0x1c ib 1 al imm8 */
|
|
{ "sbb", 0x1c, OP1F, OP_al, OP_S8, AOT_NONE },
|
|
/* SBB 0x1d iW 1 AX immW */
|
|
{ "sbb", 0x1d, OP1F, OP_AX, OP_SW, AOT_NONE },
|
|
/* SBB 0x18 /r 1 r/m8 r8 */
|
|
{ "sbb", 0x18, OP1F, OP_RM8_D0, OP_R8_R, AOT_NONE },
|
|
{ "sbb", 0x18, OP1F, OP_RM8_D8, OP_R8_R, AOT_NONE },
|
|
{ "sbb", 0x18, OP1F, OP_RM8_DW, OP_R8_R, AOT_NONE },
|
|
{ "sbb", 0x18, OP1F, OP_RM8_R8, OP_R8_R, AOT_NONE },
|
|
/* SBB 0x19 /r 1 r/mW rW */
|
|
{ "sbb", 0x19, OP1F, OP_RMW_D0, OP_RW_R, AOT_NONE },
|
|
{ "sbb", 0x19, OP1F, OP_RMW_D8, OP_RW_R, AOT_NONE },
|
|
{ "sbb", 0x19, OP1F, OP_RMW_DW, OP_RW_R, AOT_NONE },
|
|
{ "sbb", 0x19, OP1F, OP_RMW_RW, OP_RW_R, AOT_NONE },
|
|
/* SBB 0x1a /r 1 r8 r/m8 */
|
|
#if 1 /* FIXME probably doesn't work at the moment */
|
|
{ "sbb", 0x1a, OP1F, OP_RM8_R8_R,OP_RM8_D0_R,AOT_NONE },
|
|
{ "sbb", 0x1a, OP1F, OP_RM8_R8_R,OP_RM8_D8_R,AOT_NONE },
|
|
{ "sbb", 0x1a, OP1F, OP_RM8_R8_R,OP_RM8_DW_R,AOT_NONE },
|
|
{ "sbb", 0x1a, OP1F, OP_RM8_R8_R,OP_RM8_R8_R,AOT_NONE },
|
|
#endif
|
|
/* SBB 0x1b /r 1 rW r/mW */
|
|
#if 1 /* FIXME probably doesn't work at the moment */
|
|
{ "sbb", 0x1b, OP1F, OP_RMW_RW_R,OP_RMW_D0_R,AOT_NONE },
|
|
{ "sbb", 0x1b, OP1F, OP_RMW_RW_R,OP_RMW_D8_R,AOT_NONE },
|
|
{ "sbb", 0x1b, OP1F, OP_RMW_RW_R,OP_RMW_DW_R,AOT_NONE },
|
|
{ "sbb", 0x1b, OP1F, OP_RMW_RW_R,OP_RMW_RW_R,AOT_NONE },
|
|
#endif
|
|
/* SBB 0x80 /3 ib 1 r/m8 imm8 */
|
|
{ "sbbb", 0x80, OP1F, OP_RM8_D0+3,OP_S8, AOT_NONE },
|
|
{ "sbbb", 0x80, OP1F, OP_RM8_D8+3,OP_S8, AOT_NONE },
|
|
{ "sbbb", 0x80, OP1F, OP_RM8_DW+3,OP_S8, AOT_NONE },
|
|
{ "sbb", 0x80, OP1F, OP_RM8_R8+3,OP_S8, AOT_NONE },
|
|
/* SBB 0x81 /3 iW 1 r/mW immW */
|
|
{ "sbb", 0x81, OP1F, OP_RMW_D0+3,OP_SW, AOT_NONE },
|
|
{ "sbb", 0x81, OP1F, OP_RMW_D8+3,OP_SW, AOT_NONE },
|
|
{ "sbb", 0x81, OP1F, OP_RMW_DW+3,OP_SW, AOT_NONE },
|
|
{ "sbb", 0x81, OP1F, OP_RMW_RW+3,OP_SW, AOT_NONE },
|
|
/* SBB 0x83 /3 ib 1 r/mW imm8 */
|
|
{ "sbbb", 0x83, OP1F, OP_RMW_D0+3,OP_S8, AOT_NONE },
|
|
{ "sbbb", 0x83, OP1F, OP_RMW_D8+3,OP_S8, AOT_NONE },
|
|
{ "sbbb", 0x83, OP1F, OP_RMW_DW+3,OP_S8, AOT_NONE },
|
|
{ "sbb", 0x83, OP1F, OP_RMW_RW+3,OP_S8, AOT_NONE },
|
|
/* SCASB 0xae 1 */
|
|
{ "scasb", 0xae, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
#ifdef ARCH_i386_real
|
|
/* SCASW 0xaf 1 */
|
|
{ "scasw", 0xaf, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
#else
|
|
/* SCASD 0xaf 1 */
|
|
{ "scasd", 0xaf, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
#endif
|
|
/* SETcc */
|
|
/* FIXME implement */
|
|
/* SGDT 0x0f01 /0 2 m */
|
|
{ "sgdt", 0x0f01, OP2F, OP_RMW_D0+0,AOT_NONE, AOT_NONE },
|
|
{ "sgdt", 0x0f01, OP2F, OP_RMW_D8+0,AOT_NONE, AOT_NONE },
|
|
{ "sgdt", 0x0f01, OP2F, OP_RMW_DW+0,AOT_NONE, AOT_NONE },
|
|
/* SIDT 0x0f01 /1 2 m */
|
|
{ "sidt", 0x0f01, OP2F, OP_RMW_D0+1,AOT_NONE, AOT_NONE },
|
|
{ "sidt", 0x0f01, OP2F, OP_RMW_D8+1,AOT_NONE, AOT_NONE },
|
|
{ "sidt", 0x0f01, OP2F, OP_RMW_DW+1,AOT_NONE, AOT_NONE },
|
|
/* SHLD 0x0fa4 2 r/mW rW imm8 */
|
|
{ "shld", 0x0fa4, OP2F, OP_RMW_D0, OP_RW_R, OP_U8 },
|
|
{ "shld", 0x0fa4, OP2F, OP_RMW_D8, OP_RW_R, OP_U8 },
|
|
{ "shld", 0x0fa4, OP2F, OP_RMW_DW, OP_RW_R, OP_U8 },
|
|
{ "shld", 0x0fa4, OP2F, OP_RMW_RW, OP_RW_R, OP_U8 },
|
|
/* SHLD 0x0fa5 2 r/mW rW cl */
|
|
{ "shld", 0x0fa5, OP2F, OP_RMW_D0, OP_RW_R, OP_cl },
|
|
{ "shld", 0x0fa5, OP2F, OP_RMW_D8, OP_RW_R, OP_cl },
|
|
{ "shld", 0x0fa5, OP2F, OP_RMW_DW, OP_RW_R, OP_cl },
|
|
{ "shld", 0x0fa5, OP2F, OP_RMW_RW, OP_RW_R, OP_cl },
|
|
/* SHRD 0x0fac 2 r/mW rW imm8 */
|
|
{ "shrd", 0x0fac, OP2F, OP_RMW_D0, OP_RW_R, OP_U8 },
|
|
{ "shrd", 0x0fac, OP2F, OP_RMW_D8, OP_RW_R, OP_U8 },
|
|
{ "shrd", 0x0fac, OP2F, OP_RMW_DW, OP_RW_R, OP_U8 },
|
|
{ "shrd", 0x0fac, OP2F, OP_RMW_RW, OP_RW_R, OP_U8 },
|
|
/* SHRD 0x0fad 2 r/mW rW cl */
|
|
{ "shrd", 0x0fad, OP2F, OP_RMW_D0, OP_RW_R, OP_cl },
|
|
{ "shrd", 0x0fad, OP2F, OP_RMW_D8, OP_RW_R, OP_cl },
|
|
{ "shrd", 0x0fad, OP2F, OP_RMW_DW, OP_RW_R, OP_cl },
|
|
{ "shrd", 0x0fad, OP2F, OP_RMW_RW, OP_RW_R, OP_cl },
|
|
/* SLDT 0x0f00 /0 2 r/mW */
|
|
/* FIXME implement */
|
|
/* SMSW 0x0f01 /4 2 r/mW */
|
|
/* FIXME implement */
|
|
/* STC 0xf9 */
|
|
{ "stc", 0xf9, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* STD 0xfd */
|
|
{ "std", 0xfd, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* STI 0xfb */
|
|
{ "sti", 0xfb, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* STOSB 0xaa 1 */
|
|
{ "stosb", 0xaa, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
#ifdef ARCH_i386_real
|
|
/* STOSW 0xab 1 */
|
|
{ "stosw", 0xab, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
#else
|
|
/* STOSD 0xab 1 */
|
|
{ "stosd", 0xab, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
#endif
|
|
/* STR 0x0f00 /1 1 r/m16 */
|
|
/* FIXME implement */
|
|
/* SUB 0x2c ib 1 al imm8 */
|
|
{ "sub", 0x2c, OP1F, OP_al, OP_S8, AOT_NONE },
|
|
/* SUB 0x2d iW 1 AX immW */
|
|
{ "sub", 0x2d, OP1F, OP_AX, OP_SW, AOT_NONE },
|
|
/* SUB 0x28 /r 1 r/m8 r8 */
|
|
{ "sub", 0x28, OP1F, OP_RM8_D0, OP_R8_R, AOT_NONE },
|
|
{ "sub", 0x28, OP1F, OP_RM8_D8, OP_R8_R, AOT_NONE },
|
|
{ "sub", 0x28, OP1F, OP_RM8_DW, OP_R8_R, AOT_NONE },
|
|
{ "sub", 0x28, OP1F, OP_RM8_R8, OP_R8_R, AOT_NONE },
|
|
/* SUB 0x29 /r 1 r/mW rW */
|
|
{ "sub", 0x29, OP1F, OP_RMW_D0, OP_RW_R, AOT_NONE },
|
|
{ "sub", 0x29, OP1F, OP_RMW_D8, OP_RW_R, AOT_NONE },
|
|
{ "sub", 0x29, OP1F, OP_RMW_DW, OP_RW_R, AOT_NONE },
|
|
{ "sub", 0x29, OP1F, OP_RMW_RW, OP_RW_R, AOT_NONE },
|
|
/* SUB 0x2a /r 1 r8 r/m8 */
|
|
#if 1 /* FIXME probably doesn't work at the moment */
|
|
{ "sub", 0x2a, OP1F, OP_RM8_R8_R,OP_RM8_D0_R,AOT_NONE },
|
|
{ "sub", 0x2a, OP1F, OP_RM8_R8_R,OP_RM8_D8_R,AOT_NONE },
|
|
{ "sub", 0x2a, OP1F, OP_RM8_R8_R,OP_RM8_DW_R,AOT_NONE },
|
|
{ "sub", 0x2a, OP1F, OP_RM8_R8_R,OP_RM8_R8_R,AOT_NONE },
|
|
#endif
|
|
/* SUB 0x2b /r 1 rW r/mW */
|
|
#if 1 /* FIXME probably doesn't work at the moment */
|
|
{ "sub", 0x2b, OP1F, OP_RMW_RW_R,OP_RMW_D0_R,AOT_NONE },
|
|
{ "sub", 0x2b, OP1F, OP_RMW_RW_R,OP_RMW_D8_R,AOT_NONE },
|
|
{ "sub", 0x2b, OP1F, OP_RMW_RW_R,OP_RMW_DW_R,AOT_NONE },
|
|
{ "sub", 0x2b, OP1F, OP_RMW_RW_R,OP_RMW_RW_R,AOT_NONE },
|
|
#endif
|
|
/* SUB 0x80 /5 ib 1 r/m8 imm8 */
|
|
{ "subb", 0x80, OP1F, OP_RM8_D0+5,OP_S8, AOT_NONE },
|
|
{ "subb", 0x80, OP1F, OP_RM8_D8+5,OP_S8, AOT_NONE },
|
|
{ "subb", 0x80, OP1F, OP_RM8_DW+5,OP_S8, AOT_NONE },
|
|
{ "sub", 0x80, OP1F, OP_RM8_R8+5,OP_S8, AOT_NONE },
|
|
/* SUB 0x81 /5 iW 1 r/mW immW */
|
|
{ "sub", 0x81, OP1F, OP_RMW_D0+5,OP_SW, AOT_NONE },
|
|
{ "sub", 0x81, OP1F, OP_RMW_D8+5,OP_SW, AOT_NONE },
|
|
{ "sub", 0x81, OP1F, OP_RMW_DW+5,OP_SW, AOT_NONE },
|
|
{ "sub", 0x81, OP1F, OP_RMW_RW+5,OP_SW, AOT_NONE },
|
|
/* SUB 0x83 /5 ib 1 r/mW imm8 */
|
|
{ "subb", 0x83, OP1F, OP_RMW_D0+5,OP_S8, AOT_NONE },
|
|
{ "subb", 0x83, OP1F, OP_RMW_D8+5,OP_S8, AOT_NONE },
|
|
{ "subb", 0x83, OP1F, OP_RMW_DW+5,OP_S8, AOT_NONE },
|
|
{ "sub", 0x83, OP1F, OP_RMW_RW+5,OP_S8, AOT_NONE },
|
|
/* TEST 0xa8 ib 1 al imm8 */
|
|
{ "test", 0xa8, OP1F, OP_al, OP_S8, AOT_NONE },
|
|
/* TEST 0xa9 iW 1 AX immW */
|
|
{ "test", 0xa9, OP1F, OP_AX, OP_SW, AOT_NONE },
|
|
/* TEST 0xf6 /0 ib 1 r/m8 imm8 */
|
|
{ "testb", 0xf6, OP1F, OP_RM8_D0+0,OP_S8, AOT_NONE },
|
|
{ "testb", 0xf6, OP1F, OP_RM8_D8+0,OP_S8, AOT_NONE },
|
|
{ "testb", 0xf6, OP1F, OP_RM8_DW+0,OP_S8, AOT_NONE },
|
|
{ "test", 0xf6, OP1F, OP_RM8_R8+0,OP_S8, AOT_NONE },
|
|
/* TEST 0xf7 /0 iW 1 r/mW immW */
|
|
{ "test", 0xf7, OP1F, OP_RMW_D0+0,OP_SW, AOT_NONE },
|
|
{ "test", 0xf7, OP1F, OP_RMW_D8+0,OP_SW, AOT_NONE },
|
|
{ "test", 0xf7, OP1F, OP_RMW_DW+0,OP_SW, AOT_NONE },
|
|
{ "test", 0xf7, OP1F, OP_RMW_RW+0,OP_SW, AOT_NONE },
|
|
/* TEST 0x84 /r 1 r/m8 r8 */
|
|
#if 1 /* FIXME doesn't work */
|
|
{ "testb", 0x84, OP1F, OP_RM8_D0, OP_R8_R, AOT_NONE },
|
|
{ "testb", 0x84, OP1F, OP_RM8_D8, OP_R8_R, AOT_NONE },
|
|
{ "testb", 0x84, OP1F, OP_RM8_DW, OP_R8_R, AOT_NONE },
|
|
{ "test", 0x84, OP1F, OP_RM8_R8, OP_R8_R, AOT_NONE },
|
|
#endif
|
|
/* TEST 0x85 /r 1 r/mW rW */
|
|
#if 1 /* FIXME doesn't work */
|
|
{ "test", 0x85, OP1F, OP_RMW_D0, OP_RW_R, AOT_NONE },
|
|
{ "test", 0x85, OP1F, OP_RMW_D8, OP_RW_R, AOT_NONE },
|
|
{ "test", 0x85, OP1F, OP_RMW_DW, OP_RW_R, AOT_NONE },
|
|
{ "test", 0x85, OP1F, OP_RMW_RW, OP_RW_R, AOT_NONE },
|
|
#endif
|
|
/* UD2 0x0f0b 2 */
|
|
{ "ud2", 0x0f0b, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* VERR 0x0f00 /4 2 r/m16 */
|
|
/* FIXME implement */
|
|
/* VERW 0x0f00 /5 2 r/m16 */
|
|
/* FIXME implement */
|
|
/* WAIT 0x9b 1 */
|
|
{ "wait", 0x9b, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* WBINVD 0x0f09 2 */
|
|
{ "wbinvd", 0x0f09, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* WRMSR 0x0f30 2 */
|
|
{ "wrmsr", 0x0f30, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* XADD 0x0fc0 /r 2 r/m8 r8 */
|
|
{ "xadd", 0x0fc0, OP2F, OP_RM8_D0, OP_R8_R, AOT_NONE },
|
|
{ "xadd", 0x0fc0, OP2F, OP_RM8_D8, OP_R8_R, AOT_NONE },
|
|
{ "xadd", 0x0fc0, OP2F, OP_RM8_DW, OP_R8_R, AOT_NONE },
|
|
{ "xadd", 0x0fc0, OP2F, OP_RM8_R8, OP_R8_R, AOT_NONE },
|
|
/* XADD 0x0fc1 /r 2 r/mW rW */
|
|
{ "xadd", 0x0fc1, OP2F, OP_RMW_D0, OP_RW_R, AOT_NONE },
|
|
{ "xadd", 0x0fc1, OP2F, OP_RMW_D8, OP_RW_R, AOT_NONE },
|
|
{ "xadd", 0x0fc1, OP2F, OP_RMW_DW, OP_RW_R, AOT_NONE },
|
|
{ "xadd", 0x0fc1, OP2F, OP_RMW_RW, OP_RW_R, AOT_NONE },
|
|
/* XCHG 0x90 +rW 1 AX rW */
|
|
{ "xchg", 0x90, OP1F, OP_AX, OP_AX, AOT_NONE },
|
|
{ "xchg", 0x91, OP1F, OP_AX, OP_CX, AOT_NONE },
|
|
{ "xchg", 0x92, OP1F, OP_AX, OP_DX, AOT_NONE },
|
|
{ "xchg", 0x93, OP1F, OP_AX, OP_BX, AOT_NONE },
|
|
{ "xchg", 0x94, OP1F, OP_AX, OP_SP, AOT_NONE },
|
|
{ "xchg", 0x95, OP1F, OP_AX, OP_BP, AOT_NONE },
|
|
{ "xchg", 0x96, OP1F, OP_AX, OP_SI, AOT_NONE },
|
|
{ "xchg", 0x97, OP1F, OP_AX, OP_DI, AOT_NONE },
|
|
{ "xchg", 0x91, OP1F, OP_CX, OP_AX, AOT_NONE },
|
|
{ "xchg", 0x92, OP1F, OP_DX, OP_AX, AOT_NONE },
|
|
{ "xchg", 0x93, OP1F, OP_BX, OP_AX, AOT_NONE },
|
|
{ "xchg", 0x94, OP1F, OP_SP, OP_AX, AOT_NONE },
|
|
{ "xchg", 0x95, OP1F, OP_BP, OP_AX, AOT_NONE },
|
|
{ "xchg", 0x96, OP1F, OP_SI, OP_AX, AOT_NONE },
|
|
{ "xchg", 0x97, OP1F, OP_DI, OP_AX, AOT_NONE },
|
|
/* XCHG 0x86 /r 1 r/m8 r8 */
|
|
{ "xchg", 0x86, OP1F, OP_RM8_D0, OP_R8_R, AOT_NONE },
|
|
{ "xchg", 0x86, OP1F, OP_RM8_D8, OP_R8_R, AOT_NONE },
|
|
{ "xchg", 0x86, OP1F, OP_RM8_DW, OP_R8_R, AOT_NONE },
|
|
{ "xchg", 0x86, OP1F, OP_RM8_R8, OP_R8_R, AOT_NONE },
|
|
/* XCHG 0x86 /r 1 r8 r/m8 */
|
|
#if 1 /* FIXME doesn't work at the moment */
|
|
{ "xchg", 0x86, OP1F, OP_RM8_R8_R,OP_RM8_D0_R,AOT_NONE },
|
|
{ "xchg", 0x86, OP1F, OP_RM8_R8_R,OP_RM8_D8_R,AOT_NONE },
|
|
{ "xchg", 0x86, OP1F, OP_RM8_R8_R,OP_RM8_DW_R,AOT_NONE },
|
|
{ "xchg", 0x86, OP1F, OP_RM8_R8_R,OP_RM8_R8_R,AOT_NONE },
|
|
#endif
|
|
/* XCHG 0x87 /r 1 r/mW rW */
|
|
{ "xchg", 0x87, OP1F, OP_RMW_D0, OP_RW_R, AOT_NONE },
|
|
{ "xchg", 0x87, OP1F, OP_RMW_D8, OP_RW_R, AOT_NONE },
|
|
{ "xchg", 0x87, OP1F, OP_RMW_DW, OP_RW_R, AOT_NONE },
|
|
{ "xchg", 0x87, OP1F, OP_RMW_RW, OP_RW_R, AOT_NONE },
|
|
/* XCHG 0x87 /r 1 rW r/mW */
|
|
#if 1 /* FIXME doesn't work at the moment */
|
|
{ "xchg", 0x87, OP1F, OP_RMW_RW_R,OP_RMW_D0_R,AOT_NONE },
|
|
{ "xchg", 0x87, OP1F, OP_RMW_RW_R,OP_RMW_D8_R,AOT_NONE },
|
|
{ "xchg", 0x87, OP1F, OP_RMW_RW_R,OP_RMW_DW_R,AOT_NONE },
|
|
{ "xchg", 0x87, OP1F, OP_RMW_RW_R,OP_RMW_RW_R,AOT_NONE },
|
|
#endif
|
|
/* XLAT 0xd7 1 */
|
|
{ "xlat", 0xd7, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* XLATB 0xd7 1 */
|
|
{ "xlatb", 0xd7, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
|
|
/* XOR 0x34 ib 1 al imm8 */
|
|
{ "xor", 0x34, OP1F, OP_al, OP_S8, AOT_NONE },
|
|
/* XOR 0x35 iW 1 AX immW */
|
|
{ "xor", 0x35, OP1F, OP_AX, OP_SW, AOT_NONE },
|
|
/* XOR 0x30 /r 1 r/m8 r8 */
|
|
{ "xor", 0x30, OP1F, OP_RM8_D0, OP_R8_R, AOT_NONE },
|
|
{ "xor", 0x30, OP1F, OP_RM8_D8, OP_R8_R, AOT_NONE },
|
|
{ "xor", 0x30, OP1F, OP_RM8_DW, OP_R8_R, AOT_NONE },
|
|
{ "xor", 0x30, OP1F, OP_RM8_R8, OP_R8_R, AOT_NONE },
|
|
/* XOR 0x31 /r 1 r/mW rW */
|
|
{ "xor", 0x31, OP1F, OP_RMW_D0, OP_RW_R, AOT_NONE },
|
|
{ "xor", 0x31, OP1F, OP_RMW_D8, OP_RW_R, AOT_NONE },
|
|
{ "xor", 0x31, OP1F, OP_RMW_DW, OP_RW_R, AOT_NONE },
|
|
{ "xor", 0x31, OP1F, OP_RMW_RW, OP_RW_R, AOT_NONE },
|
|
/* XOR 0x32 /r 1 r8 r/m8 */
|
|
#if 1 /* FIXME doesn't work at the moment */
|
|
{ "xor", 0x32, OP1F, OP_RM8_R8_R,OP_RM8_D0_R,AOT_NONE },
|
|
{ "xor", 0x32, OP1F, OP_RM8_R8_R,OP_RM8_D8_R,AOT_NONE },
|
|
{ "xor", 0x32, OP1F, OP_RM8_R8_R,OP_RM8_DW_R,AOT_NONE },
|
|
{ "xor", 0x32, OP1F, OP_RM8_R8_R,OP_RM8_R8_R,AOT_NONE },
|
|
#endif
|
|
/* XOR 0x33 /r 1 rW r/mW */
|
|
#if 1 /* FIXME doesn't work at the moment */
|
|
{ "xor", 0x33, OP1F, OP_RMW_RW_R,OP_RMW_D0_R,AOT_NONE },
|
|
{ "xor", 0x33, OP1F, OP_RMW_RW_R,OP_RMW_D8_R,AOT_NONE },
|
|
{ "xor", 0x33, OP1F, OP_RMW_RW_R,OP_RMW_DW_R,AOT_NONE },
|
|
{ "xor", 0x33, OP1F, OP_RMW_RW_R,OP_RMW_RW_R,AOT_NONE },
|
|
#endif
|
|
/* XOR 0x80 /6 ib 1 r/m8 imm8 */
|
|
{ "xorb", 0x80, OP1F, OP_RM8_D0+6,OP_S8, AOT_NONE },
|
|
{ "xorb", 0x80, OP1F, OP_RM8_D8+6,OP_S8, AOT_NONE },
|
|
{ "xorb", 0x80, OP1F, OP_RM8_DW+6,OP_S8, AOT_NONE },
|
|
{ "xor", 0x80, OP1F, OP_RM8_R8+6,OP_S8, AOT_NONE },
|
|
/* XOR 0x81 /6 iW 1 r/mW immW */
|
|
{ "xor", 0x81, OP1F, OP_RMW_D0+6,OP_SW, AOT_NONE },
|
|
{ "xor", 0x81, OP1F, OP_RMW_D8+6,OP_SW, AOT_NONE },
|
|
{ "xor", 0x81, OP1F, OP_RMW_DW+6,OP_SW, AOT_NONE },
|
|
{ "xor", 0x81, OP1F, OP_RMW_RW+6,OP_SW, AOT_NONE },
|
|
/* XOR 0x83 /6 ib 1 r/mW imm8 */
|
|
{ "xorb", 0x83, OP1F, OP_RMW_D0+6,OP_S8, AOT_NONE },
|
|
{ "xorb", 0x83, OP1F, OP_RMW_D8+6,OP_S8, AOT_NONE },
|
|
{ "xorb", 0x83, OP1F, OP_RMW_DW+6,OP_S8, AOT_NONE },
|
|
{ "xor", 0x83, OP1F, OP_RMW_RW+6,OP_S8, AOT_NONE },
|