diff --git a/tests/verilog/Makefile.NetBSD b/tests/verilog/Makefile.NetBSD
index 0581853..74c9a36 100644
--- a/tests/verilog/Makefile.NetBSD
+++ b/tests/verilog/Makefile.NetBSD
@@ -4,6 +4,7 @@ PREFIX	= /usr/local
 DESTDIR	=
 BINDIR	= $(PREFIX)/bin
 SBINDIR	= $(PREFIX)/sbin
+VERILOG	= iverilog
 EXEEXT	=
 RM	= rm -f
 LN	= ln -f
diff --git a/tests/verilog/project.conf b/tests/verilog/project.conf
index e28fb35..a60be62 100644
--- a/tests/verilog/project.conf
+++ b/tests/verilog/project.conf
@@ -1,4 +1,5 @@
 targets=top.vhdl,top.vvp,top.fpga
+verilog=iverilog
 
 [top.fpga]
 type=object