Pierre Pronchery ff4831157d Also generate VHDL in the "verilog" test		2017-04-30 03:41:43 +02:00
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Makefile.NetBSD	Also generate VHDL in the "verilog" test	2017-04-30 03:41:43 +02:00
project.conf	Also generate VHDL in the "verilog" test	2017-04-30 03:41:43 +02:00