commit 0d88beea50c79d7739e13bcbdad3ef9143669df6
Author: Pierre Pronchery <khorben@defora.org>
Date:   Sun Apr 30 05:01:47 2017 +0200

    Initial import

diff --git a/project.conf b/project.conf
new file mode 100644
index 0000000..a132cb0
--- /dev/null
+++ b/project.conf
@@ -0,0 +1,5 @@
+package=libFPGA
+version=0.0.0
+
+subdirs=src
+dist=Makefile
diff --git a/src/counter.v b/src/counter.v
new file mode 100644
index 0000000..5fa4929
--- /dev/null
+++ b/src/counter.v
@@ -0,0 +1,57 @@
+/* $Id$ */
+/* Copyright (c) 2017 Pierre Pronchery <khorben@defora.org> */
+/* This file is part of DeforaOS libFPGA */
+/* All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+
+
+
+`ifndef COUNTER_SIZE
+ `define COUNTER_SIZE	8
+`endif
+`define COUNTER_SIZE_REG(width) (width - 1)
+
+
+module counter (
+	input wire clk,
+	input wire rst,
+	input wire en,
+	output reg [`COUNTER_SIZE_REG(`COUNTER_SIZE):0] cnt = `COUNTER_SIZE'b0
+);
+
+
+always @(posedge clk)
+begin
+	if(rst)
+	begin
+		cnt <= `COUNTER_SIZE'b0;
+	end
+	else if(en)
+	begin
+		cnt <= cnt + `COUNTER_SIZE'b1;
+	end
+end
+
+endmodule
diff --git a/src/project.conf b/src/project.conf
new file mode 100644
index 0000000..f3259d6
--- /dev/null
+++ b/src/project.conf
@@ -0,0 +1,6 @@
+targets=counter.vvp
+dist=Makefile
+
+[counter.vvp]
+type=object
+sources=counter.v