Specify the verilog program
This helps configure and build libFPGA by default for the moment.
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targets=counter.vvp,delay.vvp
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targets=counter.vvp,delay.vvp
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dist=Makefile,system.v
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dist=Makefile,system.v
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verilog=iverilog
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[counter.vvp]
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[counter.vvp]
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type=object
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type=object
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