Specify the verilog program

This helps configure and build libFPGA by default for the moment.
2017-11-09 02:18:43 +01:00 · 2017-11-09 02:18:43 +01:00 · 205c9683a0
commit 205c9683a0
parent 5e9894792d
1 changed files with 1 additions and 0 deletions
--- a/src/project.conf
+++ b/src/project.conf
@ -1,5 +1,6 @@
 targets=counter.vvp,delay.vvp
 dist=Makefile,system.v
+verilog=iverilog

 [counter.vvp]
 type=object