76 lines
2.1 KiB
Verilog
76 lines
2.1 KiB
Verilog
/* $Id$ */
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/* Copyright (c) 2017 Pierre Pronchery <khorben@defora.org> */
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/* This file is part of DeforaOS libFPGA */
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/* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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`include "system.v"
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`ifndef DELAY_TICKS
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`define DELAY_TICKS (`SYSTEM_CLOCK_HZ / 100)
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`endif
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//FIXME automatically determine the size needed
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`ifndef DELAY_SIZE
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`define DELAY_SIZE 20
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`endif
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`define DELAY_SIZE_REG(width) (width - 1)
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module delay (
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input wire clk,
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input wire rst,
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input wire en,
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output reg line = 1'b0
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);
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//variables
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reg [`DELAY_SIZE_REG(`DELAY_SIZE):0] delay_cnt = `DELAY_SIZE'b0;
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always @(posedge clk)
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begin
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if(rst)
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begin
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line <= 1'b0;
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delay_cnt <= `DELAY_SIZE'b0;
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end
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else if(en)
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begin
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delay_cnt <= delay_cnt + `DELAY_SIZE'b1;
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line <= 1'b0;
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if(delay_cnt == `DELAY_TICKS)
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begin
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line <= 1'b1;
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delay_cnt <= `DELAY_SIZE'b0;
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end
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end
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end
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endmodule
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