Added the "fdivr" and "fdivrp" instructions
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@ -415,7 +415,40 @@
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{ "fclex", 0x9bdbe2, OP3F, AOT_NONE, AOT_NONE, AOT_NONE },
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/* FCMOVcc */
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/* FIXME implement */
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/* FFREE 0xddc0 + i 2 */
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/* FDIVR 0xd8 /7 1 m32real */
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/* FIXME implement */
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/* FDIVR 0xdc /7 1 m64real */
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/* FIXME implement */
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/* FDIVR 0xd8f8 +i 2 st(0) st(i) */
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{ "fdivr", 0xd8f8, OP2F, OP_st0, OP_st0, AOT_NONE },
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{ "fdivr", 0xd8f9, OP2F, OP_st0, OP_st1, AOT_NONE },
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{ "fdivr", 0xd8fa, OP2F, OP_st0, OP_st2, AOT_NONE },
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{ "fdivr", 0xd8fb, OP2F, OP_st0, OP_st3, AOT_NONE },
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{ "fdivr", 0xd8fc, OP2F, OP_st0, OP_st4, AOT_NONE },
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{ "fdivr", 0xd8fd, OP2F, OP_st0, OP_st5, AOT_NONE },
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{ "fdivr", 0xd8fe, OP2F, OP_st0, OP_st6, AOT_NONE },
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{ "fdivr", 0xd8ff, OP2F, OP_st0, OP_st7, AOT_NONE },
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/* FDIVR 0xdcf0 +i 2 st(0) st(i) */
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{ "fdivr", 0xdcf0, OP2F, OP_st0, OP_st0, AOT_NONE },
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{ "fdivr", 0xdcf1, OP2F, OP_st1, OP_st0, AOT_NONE },
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{ "fdivr", 0xdcf2, OP2F, OP_st2, OP_st0, AOT_NONE },
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{ "fdivr", 0xdcf3, OP2F, OP_st3, OP_st0, AOT_NONE },
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{ "fdivr", 0xdcf4, OP2F, OP_st4, OP_st0, AOT_NONE },
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{ "fdivr", 0xdcf5, OP2F, OP_st5, OP_st0, AOT_NONE },
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{ "fdivr", 0xdcf6, OP2F, OP_st6, OP_st0, AOT_NONE },
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{ "fdivr", 0xdcf7, OP2F, OP_st7, OP_st0, AOT_NONE },
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/* FDIVRP 0xdef1 2 */
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{ "fdivrp", 0xdef1, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
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/* FDIVRP 0xdef0 +i 2 st(0) st(i) */
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{ "fdivrp", 0xdef0, OP2F, OP_st0, OP_st0, AOT_NONE },
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{ "fdivrp", 0xdef1, OP2F, OP_st1, OP_st0, AOT_NONE },
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{ "fdivrp", 0xdef2, OP2F, OP_st2, OP_st0, AOT_NONE },
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{ "fdivrp", 0xdef3, OP2F, OP_st3, OP_st0, AOT_NONE },
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{ "fdivrp", 0xdef4, OP2F, OP_st4, OP_st0, AOT_NONE },
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{ "fdivrp", 0xdef5, OP2F, OP_st5, OP_st0, AOT_NONE },
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{ "fdivrp", 0xdef6, OP2F, OP_st6, OP_st0, AOT_NONE },
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{ "fdivrp", 0xdef7, OP2F, OP_st7, OP_st0, AOT_NONE },
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/* FFREE 0xddc0 +i 2 st(i) */
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{ "ffree", 0xddc0, OP2F, OP_st0, AOT_NONE, AOT_NONE },
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{ "ffree", 0xddc1, OP2F, OP_st1, AOT_NONE, AOT_NONE },
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{ "ffree", 0xddc2, OP2F, OP_st2, AOT_NONE, AOT_NONE },
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@ -428,6 +461,10 @@
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/* FIXME implement */
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/* FIADD 0xde /0 1 m64int */
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/* FIXME implement */
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/* FIDIVR 0xda /7 1 m32int */
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/* FIXME implement */
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/* FIDIVR 0xde /7 1 m64int */
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/* FIXME implement */
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/* FILD 0xdf /0 1 m16int */
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/* FIXME implement */
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/* FILD 0xdb /0 1 m32int */
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25
test/i386.S
25
test/i386.S
@ -142,6 +142,31 @@
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faddp %st7, %st0
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fchs
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fclex
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fdivr %st0, %st0
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fdivr %st0, %st1
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fdivr %st0, %st2
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fdivr %st0, %st3
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fdivr %st0, %st4
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fdivr %st0, %st5
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fdivr %st0, %st6
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fdivr %st0, %st7
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fdivr %st0, %st0
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fdivr %st1, %st0
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fdivr %st2, %st0
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fdivr %st3, %st0
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fdivr %st4, %st0
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fdivr %st5, %st0
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fdivr %st6, %st0
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fdivr %st7, %st0
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fdivrp
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fdivrp %st0, %st0
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fdivrp %st1, %st0
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fdivrp %st2, %st0
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fdivrp %st3, %st0
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fdivrp %st4, %st0
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fdivrp %st5, %st0
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fdivrp %st6, %st0
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fdivrp %st7, %st0
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ffree %st0 /* dd c0 */
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ffree %st1 /* dd c1 */
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ffree %st2 /* dd c2 */
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