DeforaOS/Asm
DeforaOS/Asm
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Added the "sub" instruction

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This commit is contained in:
Pierre Pronchery 2011-04-18 05:41:13 +00:00
parent 3761dfe72e
commit 06170c28f6
1 changed files with 63 additions and 20 deletions
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83
src/arch/i386.ins
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@ -109,6 +109,10 @@
{ "aam", 0xd40a, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
{ "aam", 0xd4, OP1F, OP_U8, AOT_NONE, AOT_NONE },
{ "aas", 0x3f, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
/* ADC 0x14 ib 1 al imm8 */
{ "adc", 0x14, OP1F, OP_al, OP_S8, AOT_NONE },
/* ADC 0x15 iW 1 AX immW */
{ "adc", 0x15, OP1F, OP_AX, OP_SW, AOT_NONE },
/* ADC 0x10 /r 1 r/m8 r8 */
{ "adc", 0x10, OP1F, OP_RM8_D0_R,OP_R8, AOT_NONE },
{ "adc", 0x10, OP1F, OP_RM8_D8_R,OP_R8, AOT_NONE },
@ -133,16 +137,12 @@
{ "adc", 0x13, OP1F, OP_RMW_RW_R,OP_RMW_DW_R,AOT_NONE },
{ "adc", 0x13, OP1F, OP_RMW_RW_R,OP_RMW_RW_R,AOT_NONE },
#endif
/* ADC 0x14 ib 1 al imm8 */
{ "adc", 0x14, OP1F, OP_al, OP_S8, AOT_NONE },
/* ADC 0x15 iW 1 AX immW */
{ "adc", 0x15, OP1F, OP_AX, OP_SW, AOT_NONE },
/* ADC 0x80 /2 ib 1 r/m8 imm8 */
{ "adcb", 0x80, OP1F, OP_RM8_D0+2,OP_S8, AOT_NONE },
{ "adcb", 0x80, OP1F, OP_RM8_D8+2,OP_S8, AOT_NONE },
{ "adcb", 0x80, OP1F, OP_RM8_DW+2,OP_S8, AOT_NONE },
{ "adc", 0x80, OP1F, OP_RM8_R8+2,OP_S8, AOT_NONE },
/* ADC 0x81 /2 iW 1 r/mW imm8 */
/* ADC 0x81 /2 iW 1 r/mW immW */
{ "adc", 0x81, OP1F, OP_RMW_D0+2,OP_SW, AOT_NONE },
{ "adc", 0x81, OP1F, OP_RMW_D8+2,OP_SW, AOT_NONE },
{ "adc", 0x81, OP1F, OP_RMW_DW+2,OP_SW, AOT_NONE },
@ -152,6 +152,10 @@
{ "adcb", 0x83, OP1F, OP_RMW_D8+2,OP_S8, AOT_NONE },
{ "adcb", 0x83, OP1F, OP_RMW_DW+2,OP_S8, AOT_NONE },
{ "adc", 0x83, OP1F, OP_RMW_RW+2,OP_S8, AOT_NONE },
/* ADD 0x04 ib 1 al imm8 */
{ "add", 0x04, OP1F, OP_al, OP_S8, AOT_NONE },
/* ADD 0x05 iW 1 AX immW */
{ "add", 0x05, OP1F, OP_AX, OP_SW, AOT_NONE },
/* ADD 0x00 /r 1 r/m8 r8 */
{ "add", 0x00, OP1F, OP_RM8_D0_R,OP_R8, AOT_NONE },
{ "add", 0x00, OP1F, OP_RM8_D8_R,OP_R8, AOT_NONE },
@ -176,16 +180,12 @@
{ "add", 0x03, OP1F, OP_RMW_RW_R,OP_RMW_DW_R,AOT_NONE },
{ "add", 0x03, OP1F, OP_RMW_RW_R,OP_RMW_RW_R,AOT_NONE },
#endif
/* ADD 0x04 ib 1 al imm8 */
{ "add", 0x04, OP1F, OP_al, OP_S8, AOT_NONE },
/* ADD 0x05 iW 1 AX immW */
{ "add", 0x05, OP1F, OP_AX, OP_SW, AOT_NONE },
/* ADD 0x80 /0 ib 1 r/m8 imm8 */
{ "addb", 0x80, OP1F, OP_RM8_D0+0,OP_S8, AOT_NONE },
{ "addb", 0x80, OP1F, OP_RM8_D8+0,OP_S8, AOT_NONE },
{ "addb", 0x80, OP1F, OP_RM8_DW+0,OP_S8, AOT_NONE },
{ "add", 0x80, OP1F, OP_RM8_R8+0,OP_S8, AOT_NONE },
/* ADD 0x81 /0 iW 1 r/mW imm8 */
/* ADD 0x81 /0 iW 1 r/mW immW */
{ "add", 0x81, OP1F, OP_RMW_D0+0,OP_SW, AOT_NONE },
{ "add", 0x81, OP1F, OP_RMW_D8+0,OP_SW, AOT_NONE },
{ "add", 0x81, OP1F, OP_RMW_DW+0,OP_SW, AOT_NONE },
@ -195,6 +195,10 @@
{ "addb", 0x83, OP1F, OP_RMW_D8+0,OP_S8, AOT_NONE },
{ "addb", 0x83, OP1F, OP_RMW_DW+0,OP_S8, AOT_NONE },
{ "add", 0x83, OP1F, OP_RMW_RW+0,OP_S8, AOT_NONE },
/* AND 0x24 ib 1 al imm8 */
{ "and", 0x24, OP1F, OP_al, OP_S8, AOT_NONE },
/* AND 0x25 iW 1 AX immW */
{ "and", 0x25, OP1F, OP_AX, OP_SW, AOT_NONE },
/* AND 0x20 /r 1 r/m8 r8 */
{ "and", 0x20, OP1F, OP_RM8_D0_R,OP_R8, AOT_NONE },
{ "and", 0x20, OP1F, OP_RM8_D8_R,OP_R8, AOT_NONE },
@ -219,16 +223,12 @@
{ "and", 0x23, OP1F, OP_RMW_RW_R,OP_RMW_DW_R,AOT_NONE },
{ "and", 0x23, OP1F, OP_RMW_RW_R,OP_RMW_RW_R,AOT_NONE },
#endif
/* AND 0x24 ib 1 al imm8 */
{ "and", 0x24, OP1F, OP_al, OP_S8, AOT_NONE },
/* AND 0x25 iW 1 AX immW */
{ "and", 0x25, OP1F, OP_AX, OP_SW, AOT_NONE },
/* AND 0x80 /0 ib 1 r/m8 imm8 */
{ "andb", 0x80, OP1F, OP_RM8_D0+4,OP_S8, AOT_NONE },
{ "andb", 0x80, OP1F, OP_RM8_D8+4,OP_S8, AOT_NONE },
{ "andb", 0x80, OP1F, OP_RM8_DW+4,OP_S8, AOT_NONE },
{ "and", 0x80, OP1F, OP_RM8_R8+4,OP_S8, AOT_NONE },
/* AND 0x81 /0 iW 1 r/mW imm8 */
/* AND 0x81 /0 iW 1 r/mW immW */
{ "and", 0x81, OP1F, OP_RMW_D0+4,OP_SW, AOT_NONE },
{ "and", 0x81, OP1F, OP_RMW_D8+4,OP_SW, AOT_NONE },
{ "and", 0x81, OP1F, OP_RMW_DW+4,OP_SW, AOT_NONE },
@ -420,6 +420,49 @@
{ "fwait", 0x9b, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
/* NOP 0x90 1 */
{ "nop", 0x90, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
/* SUB 0x2c ib 1 al imm8 */
{ "sub", 0x2c, OP1F, OP_al, OP_S8, AOT_NONE },
/* SUB 0x2d iW 1 AX immW */
{ "sub", 0x2d, OP1F, OP_AX, OP_SW, AOT_NONE },
/* SUB 0x28 /r 1 r/m8 r8 */
{ "sub", 0x28, OP1F, OP_RM8_D0_R,OP_R8, AOT_NONE },
{ "sub", 0x28, OP1F, OP_RM8_D8_R,OP_R8, AOT_NONE },
{ "sub", 0x28, OP1F, OP_RM8_DW_R,OP_R8, AOT_NONE },
{ "sub", 0x28, OP1F, OP_RM8_R8_R,OP_R8, AOT_NONE },
/* SUB 0x29 /r 1 r/mW rW */
{ "sub", 0x29, OP1F, OP_RMW_D0_R,OP_RW, AOT_NONE },
{ "sub", 0x29, OP1F, OP_RMW_D8_R,OP_RW, AOT_NONE },
{ "sub", 0x29, OP1F, OP_RMW_DW_R,OP_RW, AOT_NONE },
{ "sub", 0x29, OP1F, OP_RMW_RW_R,OP_RW, AOT_NONE },
/* SUB 0x2a /r 1 r8 r/m8 */
#if 1 /* FIXME probably doesn't work at the moment */
{ "sub", 0x2a, OP1F, OP_RM8_R8_R,OP_RM8_D0_R,AOT_NONE },
{ "sub", 0x2a, OP1F, OP_RM8_R8_R,OP_RM8_D8_R,AOT_NONE },
{ "sub", 0x2a, OP1F, OP_RM8_R8_R,OP_RM8_DW_R,AOT_NONE },
{ "sub", 0x2a, OP1F, OP_RM8_R8_R,OP_RM8_R8_R,AOT_NONE },
#endif
/* SUB 0x2b /r 1 rW r/mW */
#if 1 /* FIXME probably doesn't work at the moment */
{ "sub", 0x2b, OP1F, OP_RMW_RW_R,OP_RMW_D0_R,AOT_NONE },
{ "sub", 0x2b, OP1F, OP_RMW_RW_R,OP_RMW_D8_R,AOT_NONE },
{ "sub", 0x2b, OP1F, OP_RMW_RW_R,OP_RMW_DW_R,AOT_NONE },
{ "sub", 0x2b, OP1F, OP_RMW_RW_R,OP_RMW_RW_R,AOT_NONE },
#endif
/* SUB 0x80 /5 ib 1 r/m8 imm8 */
{ "subb", 0x80, OP1F, OP_RM8_D0+5,OP_S8, AOT_NONE },
{ "subb", 0x80, OP1F, OP_RM8_D8+5,OP_S8, AOT_NONE },
{ "subb", 0x80, OP1F, OP_RM8_DW+5,OP_S8, AOT_NONE },
{ "sub", 0x80, OP1F, OP_RM8_R8+5,OP_S8, AOT_NONE },
/* SUB 0x81 /5 iW 1 r/mW immW */
{ "sub", 0x81, OP1F, OP_RMW_D0+5,OP_SW, AOT_NONE },
{ "sub", 0x81, OP1F, OP_RMW_D8+5,OP_SW, AOT_NONE },
{ "sub", 0x81, OP1F, OP_RMW_DW+5,OP_SW, AOT_NONE },
{ "sub", 0x81, OP1F, OP_RMW_RW+5,OP_SW, AOT_NONE },
/* SUB 0x83 /5 ib 1 r/mW imm8 */
{ "subb", 0x83, OP1F, OP_RMW_D0+5,OP_S8, AOT_NONE },
{ "subb", 0x83, OP1F, OP_RMW_D8+5,OP_S8, AOT_NONE },
{ "subb", 0x83, OP1F, OP_RMW_DW+5,OP_S8, AOT_NONE },
{ "sub", 0x83, OP1F, OP_RMW_RW+5,OP_S8, AOT_NONE },
/* TEST 0xa8 ib 1 al imm8 */
{ "test", 0xa8, OP1F, OP_al, OP_S8, AOT_NONE },
/* TEST 0xa9 iW 1 AX immW */
@ -514,6 +557,10 @@
{ "xlat", 0xd7, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
/* XLATB 0xd7 1 */
{ "xlatb", 0xd7, OP1F, AOT_NONE, AOT_NONE, AOT_NONE },
/* XOR 0x34 ib 1 al imm8 */
{ "xor", 0x34, OP1F, OP_al, OP_S8, AOT_NONE },
/* XOR 0x35 iW 1 AX immW */
{ "xor", 0x35, OP1F, OP_AX, OP_SW, AOT_NONE },
/* XOR 0x30 /r 1 r/m8 r8 */
{ "xor", 0x30, OP1F, OP_RM8_D0_R,OP_R8, AOT_NONE },
{ "xor", 0x30, OP1F, OP_RM8_D8_R,OP_R8, AOT_NONE },
@ -538,16 +585,12 @@
{ "xor", 0x33, OP1F, OP_RMW_RW_R,OP_RMW_DW_R,AOT_NONE },
{ "xor", 0x33, OP1F, OP_RMW_RW_R,OP_RMW_RW_R,AOT_NONE },
#endif
/* XOR 0x34 ib 1 al imm8 */
{ "xor", 0x34, OP1F, OP_al, OP_S8, AOT_NONE },
/* XOR 0x35 iW 1 AX immW */
{ "xor", 0x35, OP1F, OP_AX, OP_SW, AOT_NONE },
/* XOR 0x80 /6 ib 1 r/m8 imm8 */
{ "xorb", 0x80, OP1F, OP_RM8_D0+6,OP_S8, AOT_NONE },
{ "xorb", 0x80, OP1F, OP_RM8_D8+6,OP_S8, AOT_NONE },
{ "xorb", 0x80, OP1F, OP_RM8_DW+6,OP_S8, AOT_NONE },
{ "xor", 0x80, OP1F, OP_RM8_R8+6,OP_S8, AOT_NONE },
/* XOR 0x81 /6 iW 1 r/mW imm8 */
/* XOR 0x81 /6 iW 1 r/mW immW */
{ "xor", 0x81, OP1F, OP_RMW_D0+6,OP_SW, AOT_NONE },
{ "xor", 0x81, OP1F, OP_RMW_D8+6,OP_SW, AOT_NONE },
{ "xor", 0x81, OP1F, OP_RMW_DW+6,OP_SW, AOT_NONE },