Mostly fixed the Dalvik disassembly table
This commit is contained in:
parent
3a7bc16298
commit
4fd35ba7cc
@ -161,6 +161,7 @@ static int _dalvik_decode(ArchPlugin * plugin, ArchInstructionCall * call)
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{
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u16 = u8 << 8;
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if(helper->read(helper->arch, &u8, sizeof(u8)) != sizeof(u8))
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/* FIXME return "db" */
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return -1;
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u16 = _htol16(u16 | u8);
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if((ai = helper->get_instruction_by_opcode(helper->arch, 16,
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@ -24,8 +24,6 @@
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/* registers */
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#define AOF_DALVIK_REGSIZE 0x2
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#define OP_v0 AO_REGISTER(AOF_IMPLICIT, 32, REG_v0_id)
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#define OP_REGISTER AO_REGISTER(0, 32, 0)
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#define OP_REG4 AO_REGISTER(AOF_DALVIK_REGSIZE, 32, 4)
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#define OP_REG8 AO_REGISTER(AOF_DALVIK_REGSIZE, 32, 8)
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#define OP_REG16 AO_REGISTER(AOF_DALVIK_REGSIZE, 32, 16)
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@ -39,13 +37,13 @@
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{ "add-double", 0xab, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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{ "add-double/2addr", 0xcb, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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{ "add-double/2addr", 0xcb, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "add-float", 0xa6, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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{ "add-float/2addr", 0xc6, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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{ "add-float/2addr", 0xc6, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "add-int", 0x90, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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{ "add-int/2addr", 0xb0, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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{ "add-int/2addr", 0xb0, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "add-int/lit8", 0xd8, OP1F, OP_REG8, OP_REG8, OP_U8 },
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{ "add-int/lit16", 0xd0, OP1F, OP_REGISTER, OP_U16, AOT_NONE },
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{ "add-int/lit16", 0xd0, OP1F, OP_REG4, OP_REG4, OP_U16 },
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{ "add-long", 0x9b, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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{ "add-long/2addr", 0xbb, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "aget", 0x44, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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@ -56,15 +54,11 @@
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{ "aget-short", 0x4a, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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{ "aget-wide", 0x45, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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{ "and-int", 0x95, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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#if 1 /* XXX implement correctly */
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{ "and-int/2addr", 0xb5, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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#endif
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{ "and-int/lit8", 0xdd, OP1F, OP_REGISTER, OP_REGISTER, OP_U8 },
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{ "and-int/lit16", 0xd5, OP1F, OP_REGISTER, OP_U16, AOT_NONE },
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{ "and-int/lit8", 0xdd, OP1F, OP_REG8, OP_REG8, OP_U8 },
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{ "and-int/lit16", 0xd5, OP1F, OP_REG4, OP_REG4, OP_U16 },
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{ "and-long", 0xa0, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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#if 1 /* XXX implement correctly */
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{ "and-long/2addr", 0xc0, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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#endif
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{ "aput", 0x4b, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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{ "aput-boolean", 0x4e, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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{ "aput-byte", 0x4f, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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@ -72,12 +66,10 @@
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{ "aput-object", 0x4d, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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{ "aput-short", 0x51, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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{ "aput-wide", 0x4c, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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#if 1 /* XXX implement correctly */
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{ "array-length", 0x21, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "check-cast", 0x1f, OP1F, OP_REGISTER, OP_U16, AOT_NONE },
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#endif
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{ "check-cast", 0x1f, OP1F, OP_REG8, OP_U16, AOT_NONE },
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{ "cmp-long", 0x31, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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{ "cmpg-double", 0x30, OP1F, OP_REG8, OP_REGISTER, OP_REGISTER },
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{ "cmpg-double", 0x30, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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{ "cmpg-float", 0x2e, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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{ "cmpl-double", 0x2f, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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{ "cmpl-float", 0x2d, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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@ -91,20 +83,18 @@
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{ "const-wide/16", 0x16, OP1F, OP_REG8, OP_U16, AOT_NONE },
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{ "const-wide/32", 0x17, OP1F, OP_REG8, OP_U32, AOT_NONE },
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{ "div-double", 0xae, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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{ "div-double/2addr", 0xce, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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{ "div-double/2addr", 0xce, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "div-float", 0xa9, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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{ "div-float/2addr", 0xc9, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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{ "div-float/2addr", 0xc9, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "div-int", 0x93, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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#if 1 /* XXX implement correctly */
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{ "div-int/2addr", 0xb3, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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#endif
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{ "div-int/lit8", 0xdb, OP1F, OP_REGISTER, OP_REGISTER, OP_U8 },
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{ "div-int/lit16", 0xd3, OP1F, OP_REGISTER, OP_U16, AOT_NONE },
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{ "div-int/2addr", 0xb3, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "div-int/lit8", 0xdb, OP1F, OP_REG8, OP_REG8, OP_U8 },
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{ "div-int/lit16", 0xd3, OP1F, OP_REG4, OP_REG4, OP_U16 },
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{ "div-long", 0x9e, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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{ "div-long/2addr", 0xbe, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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{ "double-to-float", 0x8c, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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{ "double-to-int", 0x8a, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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{ "double-to-long", 0x8b, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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{ "div-long/2addr", 0xbe, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "double-to-float", 0x8c, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "double-to-int", 0x8a, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "double-to-long", 0x8b, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "fill-array-data", 0x26, OP1F, OP_REG8, OP_U32, AOT_NONE },
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{ "filled-new-array", 0x24, OP1F, OP_REG8, OP_U32, AOT_NONE },
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{ "filled-new-array-range",
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@ -172,61 +162,47 @@
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{ "move-result", 0x0a, OP1F, OP_REG8, AOT_NONE, AOT_NONE },
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{ "move-result-object", 0x0c, OP1F, OP_REG8, AOT_NONE, AOT_NONE },
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{ "move-result-wide", 0x0b, OP1F, OP_REG8, AOT_NONE, AOT_NONE },
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#if 1 /* XXX really implement */
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{ "move-wide", 0x04, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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#endif
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{ "move-wide/16", 0x06, OP1F, OP_REGISTER, OP_REGISTER, AOT_NONE },
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{ "move-wide/from16", 0x05, OP1F, OP_REGISTER, OP_REGISTER, AOT_NONE },
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{ "move-wide/16", 0x06, OP1F, OP_REG8, OP_REG16, AOT_NONE },
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{ "move-wide/from16", 0x05, OP1F, OP_REG8, OP_REG16, AOT_NONE },
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{ "mul-double", 0xad, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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{ "mul-double/2addr", 0xcd, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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{ "mul-double/2addr", 0xcd, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "mul-float", 0xa8, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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{ "mul-float/2addr", 0xc8, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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{ "mul-float/2addr", 0xc8, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "mul-int", 0x92, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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#if 1 /* XXX implement correctly */
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{ "mul-int/2addr", 0xb2, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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#endif
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{ "mul-int/lit8", 0xda, OP1F, OP_REGISTER, OP_REGISTER, OP_U8 },
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{ "mul-int/lit16", 0xd2, OP1F, OP_REGISTER, OP_U16, AOT_NONE },
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{ "mul-int/2addr", 0xb2, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "mul-int/lit8", 0xda, OP1F, OP_REG8, OP_REG8, OP_U8 },
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{ "mul-int/lit16", 0xd2, OP1F, OP_REG4, OP_REG4, OP_U16 },
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{ "mul-long", 0x9d, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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#if 1 /* XXX implement correctly */
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{ "mul-long/2addr", 0xbd, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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{ "neg-double", 0x80, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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{ "neg-float", 0x7f, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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{ "neg-int", 0x7b, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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{ "neg-long", 0x7d, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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{ "mul-long/2addr", 0xbd, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "neg-double", 0x80, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "neg-float", 0x7f, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "neg-int", 0x7b, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "neg-long", 0x7d, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "new-array", 0x23, OP1F, OP_REG4, OP_REG4, OP_U16 },
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{ "new-instance", 0x22, OP1F, OP_REG8, OP_U16, AOT_NONE },
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#endif
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{ "nop", 0x0000, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
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#if 1 /* XXX really implement */
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{ "nop", 0x00, OP1F, OP_U8, AOT_NONE, AOT_NONE },
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{ "not-int", 0x7c, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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{ "not-long", 0x7e, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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{ "not-int", 0x7c, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "not-long", 0x7e, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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#endif
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{ "or-int", 0x96, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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#if 1 /* XXX implement correctly */
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{ "or-int/2addr", 0xb6, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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#endif
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{ "or-int/lit8", 0xdb, OP1F, OP_REGISTER, OP_REGISTER, OP_U8 },
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{ "or-int/lit16", 0xd6, OP1F, OP_REGISTER, OP_U16, AOT_NONE },
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{ "or-int/2addr", 0xb6, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "or-int/lit8", 0xdb, OP1F, OP_REG8, OP_REG8, OP_U8 },
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{ "or-int/lit16", 0xd6, OP1F, OP_REG4, OP_REG4, OP_U16 },
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{ "or-long", 0xa1, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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#if 1 /* XXX implement correctly */
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{ "or-long/2addr", 0xc1, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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#endif
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{ "or-long/2addr", 0xc1, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "rem-double", 0xaf, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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{ "rem-double/2addr", 0xcf, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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{ "rem-double/2addr", 0xcf, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "rem-float", 0xaa, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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{ "rem-float/2addr", 0xca, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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{ "rem-float/2addr", 0xca, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "rem-int", 0x94, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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#if 1 /* XXX implement correctly */
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{ "rem-int/2addr", 0xb4, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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#endif
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{ "rem-int/lit8", 0xdc, OP1F, OP_REGISTER, OP_REGISTER, OP_U8 },
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{ "rem-int/lit16", 0xd4, OP1F, OP_REGISTER, OP_U16, AOT_NONE },
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{ "rem-int/2addr", 0xb4, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "rem-int/lit8", 0xdc, OP1F, OP_REG8, OP_REG8, OP_U8 },
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{ "rem-int/lit16", 0xd4, OP1F, OP_REG4, OP_REG4, OP_U16 },
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{ "rem-long", 0x9f, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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#if 1 /* XXX implement correctly */
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{ "rem-long/2addr", 0xbf, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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#endif
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{ "rem-long/2addr", 0xbf, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "return", 0x0f, OP1F, OP_REG8, AOT_NONE, AOT_NONE },
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{ "return-object", 0x11, OP1F, OP_REG8, AOT_NONE, AOT_NONE },
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{ "return-void", 0x0e00, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
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@ -240,23 +216,17 @@
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{ "sget-short", 0x66, OP1F, OP_REG8, OP_U16, AOT_NONE },
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{ "sget-wide", 0x61, OP1F, OP_REG8, OP_U16, AOT_NONE },
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{ "shl-int", 0x98, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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#if 1 /* XXX implement correctly */
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{ "shl-int/2addr", 0xb8, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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#endif
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{ "shl-int/lit8", 0xe0, OP1F, OP_REGISTER, OP_REGISTER, OP_U8 },
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{ "shl-int/2addr", 0xb8, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "shl-int/lit8", 0xe0, OP1F, OP_REG8, OP_REG8, OP_U8 },
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{ "shl-long", 0xa3, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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#if 1 /* XXX implement correctly */
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{ "shl-long/2addr", 0xc3, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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#endif
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{ "shl-long/2addr", 0xc3, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "shr-int", 0x99, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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#if 1 /* XXX implement correctly */
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{ "shr-int/2addr", 0xb9, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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#endif
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{ "shr-int/lit8", 0xe1, OP1F, OP_REGISTER, OP_REGISTER, OP_U8 },
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{ "shr-int/2addr", 0xb9, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "shr-int/lit8", 0xe1, OP1F, OP_REG8, OP_REG8, OP_U8 },
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{ "shr-long", 0xa4, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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{ "shr-long/2addr", 0xc4, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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#if 1 /* XXX implement correctly */
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{ "shr-long/2addr", 0xc4, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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{ "sparse-switch", 0x2c, OP1F, OP_REGISTER, OP_U32, AOT_NONE },
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{ "sparse-switch", 0x2c, OP1F, OP_REG8, OP_U32, AOT_NONE },
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#endif
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{ "sput", 0x67, OP1F, OP_REG8, OP_U16, AOT_NONE },
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{ "sput-boolean", 0x6a, OP1F, OP_REG8, OP_U16, AOT_NONE },
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@ -266,28 +236,24 @@
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{ "sput-short", 0x6d, OP1F, OP_REG8, OP_U16, AOT_NONE },
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{ "sput-wide", 0x68, OP1F, OP_REG8, OP_U16, AOT_NONE },
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{ "sub-double", 0xac, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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{ "sub-double/2addr", 0xcc, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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{ "sub-double/2addr", 0xcc, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "sub-float", 0xa7, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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{ "sub-float/2addr", 0xc7, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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{ "sub-float/2addr", 0xc7, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "sub-int", 0x91, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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#if 1 /* XXX implement correctly */
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{ "sub-int/2addr", 0xb1, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
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#endif
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{ "sub-int/lit8", 0xd9, OP1F, OP_REGISTER, OP_REGISTER, OP_U8 },
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{ "sub-int/lit16", 0xd1, OP1F, OP_REGISTER, OP_U16, AOT_NONE },
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{ "sub-int/2addr", 0xb1, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "sub-int/lit8", 0xd9, OP1F, OP_REG8, OP_REG8, OP_U8 },
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{ "sub-int/lit16", 0xd1, OP1F, OP_REG4, OP_REG4, OP_U16 },
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{ "sub-long", 0x9c, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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{ "sub-long/2addr", 0xbc, OP1F, OP_REG4, OP_REG4, AOT_NONE },
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{ "throw", 0x27, OP1F, OP_REGISTER, AOT_NONE, AOT_NONE },
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{ "throw", 0x27, OP1F, OP_REG8, AOT_NONE, AOT_NONE },
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{ "ushr-int", 0x9a, OP1F, OP_REG8, OP_REG8, OP_REG8 },
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{ "ushr-int/2addr", 0xba, OP1F, OP_REG4, OP_REG4, AOT_NONE },
|
||||
{ "ushr-int/lit8", 0xe2, OP1F, OP_REGISTER, OP_REGISTER, OP_U8 },
|
||||
{ "ushr-int/lit8", 0xe2, OP1F, OP_REG8, OP_REG8, OP_U8 },
|
||||
{ "ushr-long", 0xa5, OP1F, OP_REG8, OP_REG8, OP_REG8 },
|
||||
{ "ushr-long/2addr", 0xc5, OP1F, OP_REG4, OP_REG4, AOT_NONE },
|
||||
{ "xor-int", 0x97, OP1F, OP_REG8, OP_REG8, OP_REG8 },
|
||||
#if 1 /* XXX implement correctly */
|
||||
{ "xor-int/2addr", 0xb7, OP1F, OP_v0, OP_REGISTER, AOT_NONE },
|
||||
#endif
|
||||
{ "xor-int/lit8", 0xdf, OP1F, OP_REGISTER, OP_REGISTER, OP_U8 },
|
||||
{ "xor-int/lit16", 0xd7, OP1F, OP_REGISTER, OP_U16, AOT_NONE },
|
||||
{ "xor-int/2addr", 0xb7, OP1F, OP_REG4, OP_REG4, AOT_NONE },
|
||||
{ "xor-int/lit8", 0xdf, OP1F, OP_REG8, OP_REG8, OP_U8 },
|
||||
{ "xor-int/lit16", 0xd7, OP1F, OP_REG4, OP_REG4, OP_U16 },
|
||||
{ "xor-long", 0xa2, OP1F, OP_REG8, OP_REG8, OP_REG8 },
|
||||
{ "xor-long/2addr", 0xc2, OP1F, OP_REG4, OP_REG4, AOT_NONE },
|
||||
|
||||
Loading…
Reference in New Issue
Block a user