Disassembling i386 now has many more chances to complete
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@ -30,6 +30,8 @@ static int _i386_write(ArchPlugin * plugin, ArchInstruction * instruction,
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/* functions */
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/* i386_decode */
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static int _decode_constant(ArchPlugin * plugin, ArchInstructionCall * call,
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size_t i);
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static int _decode_dregister(ArchPlugin * plugin, ArchInstructionCall * call,
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size_t i);
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static int _decode_immediate(ArchPlugin * plugin, ArchInstructionCall * call,
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@ -91,6 +93,24 @@ static int _i386_decode(ArchPlugin * plugin, ArchInstructionCall * call)
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return 0;
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}
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static int _decode_constant(ArchPlugin * plugin, ArchInstructionCall * call,
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size_t i)
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{
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ArchOperandDefinition aod = call->operands[i].type;
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ArchOperand * ao = &call->operands[i];
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#ifdef DEBUG
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fprintf(stderr, "DEBUG: %s()\n", __func__);
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#endif
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if(AO_GET_FLAGS(aod) & AOF_IMPLICIT)
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{
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ao->type = AO_IMMEDIATE(0, 0, AO_GET_SIZE(aod));
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ao->value.immediate.value = AO_GET_VALUE(aod);
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return 0;
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}
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return -error_set_code(1, "%s", "Not implemented");
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}
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static int _decode_dregister(ArchPlugin * plugin, ArchInstructionCall * call,
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size_t i)
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{
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@ -219,7 +239,8 @@ static int _decode_operand(ArchPlugin * plugin, ArchInstructionCall * call,
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return _decode_modrm(plugin, call, i);
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switch(AO_GET_TYPE(call->operands[*i].type))
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{
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/* FIXME implement the rest */
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case AOT_CONSTANT:
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return _decode_constant(plugin, call, *i);
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case AOT_DREGISTER:
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return _decode_dregister(plugin, call, *i);
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case AOT_IMMEDIATE:
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@ -80,6 +80,14 @@
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#define OP_ebp AO_REGISTER(AOF_IMPLICIT, 32, REG_ebp_id)
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#define OP_esi AO_REGISTER(AOF_IMPLICIT, 32, REG_esi_id)
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#define OP_edi AO_REGISTER(AOF_IMPLICIT, 32, REG_edi_id)
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#define OP_cr0 AO_REGISTER(AOF_IMPLICIT, 32, REG_cr0_id)
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#define OP_cr1 AO_REGISTER(AOF_IMPLICIT, 32, REG_cr1_id)
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#define OP_cr2 AO_REGISTER(AOF_IMPLICIT, 32, REG_cr2_id)
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#define OP_cr3 AO_REGISTER(AOF_IMPLICIT, 32, REG_cr3_id)
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#define OP_cr4 AO_REGISTER(AOF_IMPLICIT, 32, REG_cr4_id)
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#define OP_cr5 AO_REGISTER(AOF_IMPLICIT, 32, REG_cr5_id)
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#define OP_cr6 AO_REGISTER(AOF_IMPLICIT, 32, REG_cr6_id)
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#define OP_cr7 AO_REGISTER(AOF_IMPLICIT, 32, REG_cr7_id)
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#define OP_st0 AO_REGISTER(AOF_IMPLICIT, 32, REG_st0_id)
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#define OP_st1 AO_REGISTER(AOF_IMPLICIT, 32, REG_st1_id)
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#define OP_st2 AO_REGISTER(AOF_IMPLICIT, 32, REG_st2_id)
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@ -280,40 +288,40 @@
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{ "bsr", 0x0fbd, OP2F, OP_RMW_RW_R,OP_RMW_RW_R,AOT_NONE },
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#endif
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/* BT 0x0fa3 2 r/mW rW */
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{ "bt", 0x0fa3, OP2F, OP_RMW_D0_R,OP_RW, AOT_NONE },
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{ "bt", 0x0fa3, OP2F, OP_RMW_D8_R,OP_RW, AOT_NONE },
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{ "bt", 0x0fa3, OP2F, OP_RMW_DW_R,OP_RW, AOT_NONE },
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{ "bt", 0x0fa3, OP2F, OP_RMW_RW_R,OP_RW, AOT_NONE },
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{ "bt", 0x0fa3, OP2F, OP_RMW_D0, OP_RW_R, AOT_NONE },
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{ "bt", 0x0fa3, OP2F, OP_RMW_D8, OP_RW_R, AOT_NONE },
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{ "bt", 0x0fa3, OP2F, OP_RMW_DW, OP_RW_R, AOT_NONE },
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{ "bt", 0x0fa3, OP2F, OP_RMW_RW, OP_RW_R, AOT_NONE },
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/* BT 0x0fba /4 ib 2 r/mW imm8 */
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{ "bt", 0x0fba, OP2F, OP_RMW_D0+4,OP_S8, AOT_NONE },
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{ "bt", 0x0fba, OP2F, OP_RMW_D8+4,OP_S8, AOT_NONE },
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{ "bt", 0x0fba, OP2F, OP_RMW_DW+4,OP_S8, AOT_NONE },
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{ "bt", 0x0fba, OP2F, OP_RMW_RW+4,OP_S8, AOT_NONE },
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/* BTC 0x0fbb 2 r/mW rW */
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{ "btc", 0x0fbb, OP2F, OP_RMW_D0_R,OP_RW, AOT_NONE },
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{ "btc", 0x0fbb, OP2F, OP_RMW_D8_R,OP_RW, AOT_NONE },
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{ "btc", 0x0fbb, OP2F, OP_RMW_DW_R,OP_RW, AOT_NONE },
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{ "btc", 0x0fbb, OP2F, OP_RMW_RW_R,OP_RW, AOT_NONE },
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{ "btc", 0x0fbb, OP2F, OP_RMW_D0, OP_RW_R, AOT_NONE },
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{ "btc", 0x0fbb, OP2F, OP_RMW_D8, OP_RW_R, AOT_NONE },
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{ "btc", 0x0fbb, OP2F, OP_RMW_DW, OP_RW_R, AOT_NONE },
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{ "btc", 0x0fbb, OP2F, OP_RMW_RW, OP_RW_R, AOT_NONE },
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/* BTC 0x0fba /7 ib 2 r/mW imm8 */
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{ "btc", 0x0fba, OP2F, OP_RMW_D0+7,OP_S8, AOT_NONE },
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{ "btc", 0x0fba, OP2F, OP_RMW_D8+7,OP_S8, AOT_NONE },
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{ "btc", 0x0fba, OP2F, OP_RMW_DW+7,OP_S8, AOT_NONE },
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{ "btc", 0x0fba, OP2F, OP_RMW_RW+7,OP_S8, AOT_NONE },
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/* BTR 0x0fb3 2 r/mW rW */
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{ "btr", 0x0fb3, OP2F, OP_RMW_D0_R,OP_RW, AOT_NONE },
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{ "btr", 0x0fb3, OP2F, OP_RMW_D8_R,OP_RW, AOT_NONE },
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{ "btr", 0x0fb3, OP2F, OP_RMW_DW_R,OP_RW, AOT_NONE },
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{ "btr", 0x0fb3, OP2F, OP_RMW_RW_R,OP_RW, AOT_NONE },
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{ "btr", 0x0fb3, OP2F, OP_RMW_D0, OP_RW_R, AOT_NONE },
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{ "btr", 0x0fb3, OP2F, OP_RMW_D8, OP_RW_R, AOT_NONE },
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{ "btr", 0x0fb3, OP2F, OP_RMW_DW, OP_RW_R, AOT_NONE },
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{ "btr", 0x0fb3, OP2F, OP_RMW_RW, OP_RW_R, AOT_NONE },
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/* BTR 0x0fba /6 ib 2 r/mW imm8 */
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{ "btr", 0x0fba, OP2F, OP_RMW_D0+6,OP_S8, AOT_NONE },
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{ "btr", 0x0fba, OP2F, OP_RMW_D8+6,OP_S8, AOT_NONE },
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{ "btr", 0x0fba, OP2F, OP_RMW_DW+6,OP_S8, AOT_NONE },
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{ "btr", 0x0fba, OP2F, OP_RMW_RW+6,OP_S8, AOT_NONE },
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/* BTS 0x0fab 2 r/mW rW */
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{ "bts", 0x0fab, OP2F, OP_RMW_D0_R,OP_RW, AOT_NONE },
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{ "bts", 0x0fab, OP2F, OP_RMW_D8_R,OP_RW, AOT_NONE },
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{ "bts", 0x0fab, OP2F, OP_RMW_DW_R,OP_RW, AOT_NONE },
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{ "bts", 0x0fab, OP2F, OP_RMW_RW_R,OP_RW, AOT_NONE },
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{ "bts", 0x0fab, OP2F, OP_RMW_D0, OP_RW_R, AOT_NONE },
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{ "bts", 0x0fab, OP2F, OP_RMW_D8, OP_RW_R, AOT_NONE },
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{ "bts", 0x0fab, OP2F, OP_RMW_DW, OP_RW_R, AOT_NONE },
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{ "bts", 0x0fab, OP2F, OP_RMW_RW, OP_RW_R, AOT_NONE },
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/* BTS 0x0fba /5 ib 2 r/mW imm8 */
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{ "bts", 0x0fba, OP2F, OP_RMW_D0+5,OP_S8, AOT_NONE },
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{ "bts", 0x0fba, OP2F, OP_RMW_D8+5,OP_S8, AOT_NONE },
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@ -748,9 +756,20 @@
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{ "mov", 0xc7, OP1F, OP_RMW_D8+0,OP_SW, AOT_NONE },
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{ "mov", 0xc7, OP1F, OP_RMW_DW+0,OP_SW, AOT_NONE },
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{ "mov", 0xc7, OP1F, OP_RMW_RW+0,OP_SW, AOT_NONE },
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#if 1 /* FIXME doesn't work properly */
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/* MOV 0x0f20 /r 2 r32 cr0-cr4 */
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/* FIXME implement */
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{ "mov", 0x0f20, OP2F, OP_RW_R, OP_cr0, AOT_NONE },
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{ "mov", 0x0f20, OP2F, OP_RW_R, OP_cr2, AOT_NONE },
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{ "mov", 0x0f20, OP2F, OP_RW_R, OP_cr3, AOT_NONE },
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{ "mov", 0x0f20, OP2F, OP_RW_R, OP_cr4, AOT_NONE },
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#endif
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#if 1 /* FIXME doesn't work properly */
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/* MOV 0x0f22 /r 2 cr0-cr4 r32 */
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{ "mov", 0x0f22, OP2F, OP_cr0, OP_RW_R, AOT_NONE },
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{ "mov", 0x0f22, OP2F, OP_cr2, OP_RW_R, AOT_NONE },
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{ "mov", 0x0f22, OP2F, OP_cr3, OP_RW_R, AOT_NONE },
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{ "mov", 0x0f22, OP2F, OP_cr4, OP_RW_R, AOT_NONE },
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#endif
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/* FIXME implement */
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/* MOV 0x0f21 /r 2 r32 dr0-dr7 */
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/* FIXME implement */
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@ -1044,25 +1063,25 @@
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{ "sidt", 0x0f01, OP2F, OP_RMW_D8+1,AOT_NONE, AOT_NONE },
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{ "sidt", 0x0f01, OP2F, OP_RMW_DW+1,AOT_NONE, AOT_NONE },
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/* SHLD 0x0fa4 2 r/mW rW imm8 */
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{ "shld", 0x0fa4, OP2F, OP_RMW_D0_R,OP_RW, OP_U8 },
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{ "shld", 0x0fa4, OP2F, OP_RMW_D8_R,OP_RW, OP_U8 },
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{ "shld", 0x0fa4, OP2F, OP_RMW_DW_R,OP_RW, OP_U8 },
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{ "shld", 0x0fa4, OP2F, OP_RMW_RW_R,OP_RW, OP_U8 },
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{ "shld", 0x0fa4, OP2F, OP_RMW_D0, OP_RW_R, OP_U8 },
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{ "shld", 0x0fa4, OP2F, OP_RMW_D8, OP_RW_R, OP_U8 },
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{ "shld", 0x0fa4, OP2F, OP_RMW_DW, OP_RW_R, OP_U8 },
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{ "shld", 0x0fa4, OP2F, OP_RMW_RW, OP_RW_R, OP_U8 },
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/* SHLD 0x0fa5 2 r/mW rW cl */
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{ "shld", 0x0fa5, OP2F, OP_RMW_D0_R,OP_RW, OP_cl },
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{ "shld", 0x0fa5, OP2F, OP_RMW_D8_R,OP_RW, OP_cl },
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{ "shld", 0x0fa5, OP2F, OP_RMW_DW_R,OP_RW, OP_cl },
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{ "shld", 0x0fa5, OP2F, OP_RMW_RW_R,OP_RW, OP_cl },
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{ "shld", 0x0fa5, OP2F, OP_RMW_D0, OP_RW_R, OP_cl },
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{ "shld", 0x0fa5, OP2F, OP_RMW_D8, OP_RW_R, OP_cl },
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{ "shld", 0x0fa5, OP2F, OP_RMW_DW, OP_RW_R, OP_cl },
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{ "shld", 0x0fa5, OP2F, OP_RMW_RW, OP_RW_R, OP_cl },
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/* SHRD 0x0fac 2 r/mW rW imm8 */
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{ "shrd", 0x0fac, OP2F, OP_RMW_D0_R,OP_RW, OP_U8 },
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{ "shrd", 0x0fac, OP2F, OP_RMW_D8_R,OP_RW, OP_U8 },
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{ "shrd", 0x0fac, OP2F, OP_RMW_DW_R,OP_RW, OP_U8 },
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{ "shrd", 0x0fac, OP2F, OP_RMW_RW_R,OP_RW, OP_U8 },
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{ "shrd", 0x0fac, OP2F, OP_RMW_D0, OP_RW_R, OP_U8 },
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{ "shrd", 0x0fac, OP2F, OP_RMW_D8, OP_RW_R, OP_U8 },
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{ "shrd", 0x0fac, OP2F, OP_RMW_DW, OP_RW_R, OP_U8 },
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{ "shrd", 0x0fac, OP2F, OP_RMW_RW, OP_RW_R, OP_U8 },
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/* SHRD 0x0fad 2 r/mW rW cl */
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{ "shrd", 0x0fad, OP2F, OP_RMW_D0_R,OP_RW, OP_cl },
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{ "shrd", 0x0fad, OP2F, OP_RMW_D8_R,OP_RW, OP_cl },
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{ "shrd", 0x0fad, OP2F, OP_RMW_DW_R,OP_RW, OP_cl },
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{ "shrd", 0x0fad, OP2F, OP_RMW_RW_R,OP_RW, OP_cl },
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{ "shrd", 0x0fad, OP2F, OP_RMW_D0, OP_RW_R, OP_cl },
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{ "shrd", 0x0fad, OP2F, OP_RMW_D8, OP_RW_R, OP_cl },
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{ "shrd", 0x0fad, OP2F, OP_RMW_DW, OP_RW_R, OP_cl },
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{ "shrd", 0x0fad, OP2F, OP_RMW_RW, OP_RW_R, OP_cl },
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/* SLDT 0x0f00 /0 2 r/mW */
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/* FIXME implement */
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/* SMSW 0x0f01 /4 2 r/mW */
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@ -1168,15 +1187,15 @@
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/* WRMSR 0x0f30 2 */
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{ "wrmsr", 0x0f30, OP2F, AOT_NONE, AOT_NONE, AOT_NONE },
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/* XADD 0x0fc0 /r 2 r/m8 r8 */
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{ "xadd", 0x0fc0, OP2F, OP_RM8_D0_R,OP_R8, AOT_NONE },
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{ "xadd", 0x0fc0, OP2F, OP_RM8_D8_R,OP_R8, AOT_NONE },
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{ "xadd", 0x0fc0, OP2F, OP_RM8_DW_R,OP_R8, AOT_NONE },
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{ "xadd", 0x0fc0, OP2F, OP_RM8_R8_R,OP_R8, AOT_NONE },
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{ "xadd", 0x0fc0, OP2F, OP_RM8_D0, OP_R8_R, AOT_NONE },
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{ "xadd", 0x0fc0, OP2F, OP_RM8_D8, OP_R8_R, AOT_NONE },
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{ "xadd", 0x0fc0, OP2F, OP_RM8_DW, OP_R8_R, AOT_NONE },
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{ "xadd", 0x0fc0, OP2F, OP_RM8_R8, OP_R8_R, AOT_NONE },
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/* XADD 0x0fc1 /r 2 r/mW rW */
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{ "xadd", 0x0fc1, OP2F, OP_RMW_D0_R,OP_RW, AOT_NONE },
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{ "xadd", 0x0fc1, OP2F, OP_RMW_D8_R,OP_RW, AOT_NONE },
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{ "xadd", 0x0fc1, OP2F, OP_RMW_DW_R,OP_RW, AOT_NONE },
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{ "xadd", 0x0fc1, OP2F, OP_RMW_RW_R,OP_RW, AOT_NONE },
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{ "xadd", 0x0fc1, OP2F, OP_RMW_D0, OP_RW_R, AOT_NONE },
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{ "xadd", 0x0fc1, OP2F, OP_RMW_D8, OP_RW_R, AOT_NONE },
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{ "xadd", 0x0fc1, OP2F, OP_RMW_DW, OP_RW_R, AOT_NONE },
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{ "xadd", 0x0fc1, OP2F, OP_RMW_RW, OP_RW_R, AOT_NONE },
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/* XCHG 0x90 +rW 1 AX rW */
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{ "xchg", 0x90, OP1F, OP_AX, OP_AX, AOT_NONE },
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{ "xchg", 0x91, OP1F, OP_AX, OP_CX, AOT_NONE },
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@ -31,6 +31,14 @@ REG(edi,32, 0x05)
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REG(esp,32, 0x06)
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REG(ebp,32, 0x07)
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#endif /* !ARCH_i386_real */
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REG(cr0,32, 0x00)
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REG(cr1,32, 0x01)
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REG(cr2,32, 0x02)
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REG(cr3,32, 0x03)
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REG(cr4,32, 0x04)
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REG(cr5,32, 0x05)
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REG(cr6,32, 0x06)
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REG(cr7,32, 0x07)
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REG(st0,32, 0x08)
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REG(st1,32, 0x09)
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REG(st2,32, 0x0a)
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