Began to implement ARM de-assembly
This commit is contained in:
parent
d2186c0463
commit
b57fb7603c
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@ -1,5 +1,5 @@
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/* $Id$ */
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/* Copyright (c) 2011 Pierre Pronchery <khorben@defora.org> */
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/* Copyright (c) 2011-2012 Pierre Pronchery <khorben@defora.org> */
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/* This file is part of DeforaOS Devel asm */
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/* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -77,5 +77,5 @@ AsmArchPlugin arch_plugin =
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NULL,
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NULL,
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_arm_encode,
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NULL
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_arm_decode
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};
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237
src/arch/arm.h
237
src/arch/arm.h
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@ -22,12 +22,243 @@
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/* private */
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/* prototypes */
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/* plug-in */
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static int _arm_decode(AsmArchPlugin * plugin, AsmArchInstructionCall * call);
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static int _arm_encode(AsmArchPlugin * plugin, AsmArchInstruction * instruction,
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AsmArchInstructionCall * call);
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/* functions */
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/* plug-in */
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/* arm_decode */
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static void _decode_reg_reg_dreg(AsmArchPlugin * plugin,
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AsmArchInstructionCall * call, uint32_t opcode);
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static void _decode_reg_reg_reg(AsmArchPlugin * plugin,
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AsmArchInstructionCall * call, uint32_t opcode);
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static void _decode_reg_reg_u12(AsmArchPlugin * plugin,
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AsmArchInstructionCall * call, uint32_t opcode);
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static void _decode_u24(AsmArchInstructionCall * call, uint32_t opcode);
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static void _decode_u4_u4_reg(AsmArchPlugin * plugin,
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AsmArchInstructionCall * call, uint32_t opcode);
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static int _decode_unknown(AsmArchInstructionCall * call, uint32_t opcode);
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static int _arm_decode(AsmArchPlugin * plugin, AsmArchInstructionCall * call)
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{
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AsmArchPluginHelper * helper = plugin->helper;
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uint32_t opcode;
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uint32_t op;
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AsmArchInstruction * ai;
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/* read 4 bytes in the proper endian */
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if(helper->read(helper->arch, &opcode, sizeof(opcode))
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!= sizeof(opcode))
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return -1;
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#if 1
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/* FIXME apply as relevant */
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opcode = _htob32(opcode);
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#endif
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/* lookup the instruction */
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/* FIXME decode everything in the proper order */
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/* bits 27, 26, 25 and 24 are set */
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if((op = (opcode & OPSI(0x0))) == OPSI(0x0))
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{
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ai = helper->get_instruction_by_opcode(helper->arch, 32,
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opcode & OPSI(0xf));
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_decode_u24(call, opcode);
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}
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/* bits 27, 26, 25 are set */
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else if((op = (opcode & OPCDO(0x0))) == OPCDO(0x0))
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{
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ai = helper->get_instruction_by_opcode(helper->arch, 32,
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opcode & OPCDO(0xf));
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_decode_u4_u4_reg(plugin, call, opcode);
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}
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/* bits 27, 25, 24 are set */
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else if((op = (opcode & OPBL(0x0))) == OPBL(0x0))
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ai = helper->get_instruction_by_opcode(helper->arch, 32,
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opcode & OPBL(0xf));
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/* bits 27, 25 are set */
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else if((op = (opcode & OPB(0x0))) == OPB(0x0))
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ai = helper->get_instruction_by_opcode(helper->arch, 32,
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opcode & OPB(0xf));
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/* bits 26, 25, 22, 20 */
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else if((op = (opcode & OPSDTLB(0x0))) == OPSDTLB(0x0))
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ai = helper->get_instruction_by_opcode(helper->arch, 32,
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opcode & OPSDTLB(0xf));
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/* bits 26, 25, 22 are set */
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else if((op = (opcode & OPSDTSB(0x0))) == OPSDTSB(0x0))
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ai = helper->get_instruction_by_opcode(helper->arch, 32,
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opcode & OPSDTSB(0xf));
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/* bits 26, 25, 20 are set */
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else if((op = (opcode & OPSDTL(0x0))) == OPSDTL(0x0))
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ai = helper->get_instruction_by_opcode(helper->arch, 32,
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opcode & OPSDTL(0xf));
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/* bits 26, 25 are set */
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else if((op = (opcode & OPSDTS(0x0))) == OPSDTS(0x0))
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ai = helper->get_instruction_by_opcode(helper->arch, 32,
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opcode & OPSDTS(0xf));
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/* bits 25, 20 are set */
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else if((op = (opcode & OPDPIS(0x0, 0x0))) == OPDPIS(0x0, 0x0))
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{
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ai = helper->get_instruction_by_opcode(helper->arch, 32,
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opcode & OPDPIS(0xf, 0xf));
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_decode_reg_reg_u12(plugin, call, opcode);
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}
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/* bit 25 is set */
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else if((op = (opcode & OPDPI(0x0, 0x0))) == OPDPI(0x0, 0x0))
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{
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ai = helper->get_instruction_by_opcode(helper->arch, 32,
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opcode & OPDPI(0xf, 0xf));
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_decode_reg_reg_u12(plugin, call, opcode);
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}
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/* bits 24, 22 are set */
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else if((op = (opcode & OPSDSB(0x0))) == OPSDSB(0x0))
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{
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ai = helper->get_instruction_by_opcode(helper->arch, 32,
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opcode & OPSDSB(0xf));
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_decode_reg_reg_dreg(plugin, call, opcode);
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}
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/* bit 24 is set */
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else if((op = (opcode & OPPTI(0x0))) == OPPTI(0x0))
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ai = helper->get_instruction_by_opcode(helper->arch, 32,
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opcode & OPPTI(0xf));
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/* bit 24 is set */
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else if((op = (opcode & OPPT(0x0))) == OPPT(0x0))
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ai = helper->get_instruction_by_opcode(helper->arch, 32,
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opcode & OPPT(0xf));
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/* bit 24 is set */
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else if((op = (opcode & OPSDS(0x0))) == OPSDS(0x0))
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{
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ai = helper->get_instruction_by_opcode(helper->arch, 32,
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opcode & OPSDS(0xf));
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_decode_reg_reg_dreg(plugin, call, opcode);
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}
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/* bits 21, 20, 8 and 4 are set */
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else if((op = (opcode & OPMULAS(0x0))) == OPMULAS(0x0))
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ai = helper->get_instruction_by_opcode(helper->arch, 32,
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opcode & OPMULAS(0xf));
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/* bits 4, 5, 6, 7, 8, 9, 10, 12, 12, 13, 14, 15, 16, 18, 21 are set */
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else if((op = (opcode & OPBX(0x0))) == OPBX(0x0))
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ai = helper->get_instruction_by_opcode(helper->arch, 32,
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opcode & OPBX(0xf));
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/* bits 21, 8 and 4 are set */
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else if((op = (opcode & OPMULA(0x0))) == OPMULA(0x0))
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ai = helper->get_instruction_by_opcode(helper->arch, 32,
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opcode & OPMULA(0xf));
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/* bits 20, 8 and 4 are set */
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else if((op = (opcode & OPMULS(0x0))) == OPMULS(0x0))
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ai = helper->get_instruction_by_opcode(helper->arch, 32,
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opcode & OPMULS(0xf));
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/* bit 20 is set */
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else if((op = (opcode & OPDPS(0x0, 0x0))) == OPDPS(0x0, 0x0))
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{
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ai = helper->get_instruction_by_opcode(helper->arch, 32,
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opcode & OPDPS(0xf, 0xf));
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_decode_reg_reg_reg(plugin, call, opcode);
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}
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/* bits 8 and 4 are set */
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else if((op = (opcode & OPMUL(0x0))) == OPMUL(0x0))
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{
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ai = helper->get_instruction_by_opcode(helper->arch, 32,
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opcode & OPMUL(0xf));
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_decode_reg_reg_reg(plugin, call, opcode);
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}
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/* no bits set */
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else if((op = (opcode & OPDP(0x0, 0x0))) == OPDP(0x0, 0x0))
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{
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ai = helper->get_instruction_by_opcode(helper->arch, 32,
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opcode & OPDP(0xf, 0xf));
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_decode_reg_reg_reg(plugin, call, opcode);
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}
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else
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/* unknown instruction */
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return _decode_unknown(call, opcode);
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call->name = ai->name;
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call->operands_cnt = 0;
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if((call->operands[0].definition = ai->op1) != AOT_NONE)
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call->operands_cnt++;
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if((call->operands[1].definition = ai->op2) != AOT_NONE)
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call->operands_cnt++;
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if((call->operands[2].definition = ai->op3) != AOT_NONE)
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call->operands_cnt++;
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return 0;
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}
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static void _decode_reg_reg_dreg(AsmArchPlugin * plugin,
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AsmArchInstructionCall * call, uint32_t opcode)
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{
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AsmArchPluginHelper * helper = plugin->helper;
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AsmArchRegister * ar;
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if((ar = helper->get_register_by_id_size(helper->arch,
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(opcode >> 12) & 0xf, 32)) != NULL)
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call->operands[0].value._register.name = ar->name;
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if((ar = helper->get_register_by_id_size(helper->arch,
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(opcode >> 16) & 0xf, 32)) != NULL)
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call->operands[1].value._register.name = ar->name;
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if((ar = helper->get_register_by_id_size(helper->arch,
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opcode & 0xf, 32)) != NULL)
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call->operands[2].value.dregister.name = ar->name;
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}
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static void _decode_reg_reg_reg(AsmArchPlugin * plugin,
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AsmArchInstructionCall * call, uint32_t opcode)
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{
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AsmArchPluginHelper * helper = plugin->helper;
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AsmArchRegister * ar;
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if((ar = helper->get_register_by_id_size(helper->arch,
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(opcode >> 12) & 0xf, 32)) != NULL)
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call->operands[0].value._register.name = ar->name;
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if((ar = helper->get_register_by_id_size(helper->arch,
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(opcode >> 16) & 0xf, 32)) != NULL)
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call->operands[1].value._register.name = ar->name;
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if((ar = helper->get_register_by_id_size(helper->arch,
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opcode & 0xf, 32)) != NULL)
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call->operands[2].value._register.name = ar->name;
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}
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static void _decode_reg_reg_u12(AsmArchPlugin * plugin,
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AsmArchInstructionCall * call, uint32_t opcode)
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{
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AsmArchPluginHelper * helper = plugin->helper;
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AsmArchRegister * ar;
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if((ar = helper->get_register_by_id_size(helper->arch,
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(opcode >> 12) & 0xf, 32)) != NULL)
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call->operands[0].value._register.name = ar->name;
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if((ar = helper->get_register_by_id_size(helper->arch,
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(opcode >> 16) & 0xf, 32)) != NULL)
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call->operands[1].value._register.name = ar->name;
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call->operands[2].value.immediate.value = opcode & 0xfff;
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}
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static void _decode_u24(AsmArchInstructionCall * call, uint32_t opcode)
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{
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call->operands[0].value.immediate.value = opcode & 0x00ffffff;
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}
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static void _decode_u4_u4_reg(AsmArchPlugin * plugin,
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AsmArchInstructionCall * call, uint32_t opcode)
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{
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AsmArchPluginHelper * helper = plugin->helper;
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AsmArchRegister * ar;
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/* FIXME implement u4 and u4 */
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if((ar = helper->get_register_by_id_size(helper->arch,
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(opcode >> 12) & 0xf, 32)) != NULL)
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call->operands[2].value._register.name = ar->name;
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}
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static int _decode_unknown(AsmArchInstructionCall * call, uint32_t opcode)
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{
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call->name = "dw";
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call->operands[0].definition = AO_IMMEDIATE(0, 32, 0);
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call->operands[0].value.immediate.value = opcode;
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call->operands_cnt = 1;
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return 0;
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}
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/* arm_encode */
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static int _arm_encode(AsmArchPlugin * plugin, AsmArchInstruction * instruction,
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AsmArchInstructionCall * call)
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@ -37,7 +268,7 @@ static int _arm_encode(AsmArchPlugin * plugin, AsmArchInstruction * instruction,
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AsmArchRegister * ar;
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char const * p;
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switch(instruction->opcode & 0x0fffffff) /* ignore condition code */
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switch(opcode & 0x0fffffff) /* ignore condition code */
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{
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/* branch, branch with link */
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case OPB(0): /* b */
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@ -356,6 +587,10 @@ static int _arm_encode(AsmArchPlugin * plugin, AsmArchInstruction * instruction,
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break;
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#endif
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}
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#if 1
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/* FIXME apply as relevant */
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opcode = _htob32(opcode);
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#endif
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if(helper->write(helper->arch, &opcode, sizeof(opcode))
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!= sizeof(opcode))
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return -1;
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118
src/arch/arm.ins
118
src/arch/arm.ins
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@ -17,21 +17,21 @@
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/* generic */
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/* conditions */
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#define eq (0x0 << 28)
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#define ne (0x1 << 28)
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#define cs (0x2 << 28)
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#define cc (0x3 << 28)
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#define mi (0x4 << 28)
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#define pl (0x5 << 28)
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#define vs (0x6 << 28)
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#define vc (0x7 << 28)
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#define hi (0x8 << 28)
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#define ls (0x9 << 28)
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#define ge (0xa << 28)
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#define lt (0xb << 28)
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#define gt (0xc << 28)
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#define le (0xd << 28)
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#define al (0xe << 28)
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#define eq 0x0
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#define ne 0x1
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#define cs 0x2
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#define cc 0x3
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#define mi 0x4
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#define pl 0x5
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#define vs 0x6
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#define vc 0x7
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#define hi 0x8
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#define ls 0x9
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#define ge 0xa
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#define lt 0xb
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#define gt 0xc
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#define le 0xd
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#define al 0xe
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/* opcodes */
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#define OPNOP AO_IMMEDIATE(0, 32, 0)
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@ -41,114 +41,114 @@
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#define OP_R_SPSR AO_REGISTER(AOF_IMPLICIT, 32, REG_spsr_id)
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/* block data transfer */
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#define OPBDTL(cond) (cond | (0x4 << 25) | (0x1 << 20))
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#define OPBDTL(cond) ((cond << 28) | (0x4 << 25) | (0x1 << 20))
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#define OPBDTLF (32 << AOD_SIZE)
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#define OPBDT_U16 AO_IMMEDIATE(0, 16, 0)
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#define OPBDTS(cond) (cond | (0x4 << 25))
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#define OPBDTS(cond) ((cond << 28) | (0x4 << 25))
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#define OPBDTSF (32 << AOD_SIZE)
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/* branch, branch with link */
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#define OPB(cond) (cond | (0x5 << 25))
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#define OPB(cond) ((cond << 28) | (0x5 << 25))
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#define OPBF (32 << AOD_SIZE)
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#define OPB_S26 AO_IMMEDIATE(AOF_SIGNED, 26, 0)
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#define OPBL(cond) (cond | (0x5 << 25) | (0x1 << 24))
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#define OPBL(cond) ((cond << 28) | (0x5 << 25) | (0x1 << 24))
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#define OPBLF (32 << AOD_SIZE)
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#define OPBL_S26 AO_IMMEDIATE(AOF_SIGNED, 26, 0)
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/* branch and exchange */
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#define OPBX(cond) (cond | (0x12fff1 << 4))
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#define OPBX(cond) ((cond << 28) | (0x12fff1 << 4))
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#define OPBXF (32 << AOD_SIZE)
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/* coprocessor data operation */
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#define OPCDO(cond) (cond | (0xe << 24))
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#define OPCDO(cond) ((cond << 28) | (0xe << 24))
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#define OPCDOF (32 << AOD_SIZE)
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#define OPCDO_U4 AO_IMMEDIATE(0, 4, 0)
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/* coprocessor data transfers */
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#define OPCDTL(cond) (cond | (0x6 << 25) | (0x1 << 20))
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#define OPCDTL(cond) ((cond << 28) | (0x6 << 25) | (0x1 << 20))
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#define OPCDTLF (32 << AOD_SIZE)
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#define OPCDTL_U4 AO_IMMEDIATE(0, 4, 0)
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#define OPCDTL_U8 AO_IMMEDIATE(0, 8, 0)
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#define OPCDTS(cond) (cond | (0x6 << 25))
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#define OPCDTS(cond) ((cond << 28) | (0x6 << 25))
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#define OPCDTSF (32 << AOD_SIZE)
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#define OPCDTS_U4 AO_IMMEDIATE(0, 4, 0)
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#define OPCDTS_U8 AO_IMMEDIATE(0, 8, 0)
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/* coprocessor register transfers */
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#define OPCRTL(cond) (cond | (0xe << 24) | (0x1 << 20) | (0x1 << 4))
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#define OPCRTL(cond) ((cond << 28) | (0xe << 24) | (0x1 << 20) | (0x1 << 4))
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#define OPCRTLF (32 << AOD_SIZE)
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#define OPCRTL_U3 AO_IMMEDIATE(0, 3, 0)
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#define OPCRTL_U4 AO_IMMEDIATE(0, 4, 0)
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#define OPCRTS(cond) (cond | (0xe << 24) | (0x1 << 4))
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#define OPCRTS(cond) ((cond << 28) | (0xe << 24) | (0x1 << 4))
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#define OPCRTSF (32 << AOD_SIZE)
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#define OPCRTS_U3 AO_IMMEDIATE(0, 3, 0)
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#define OPCRTS_U4 AO_IMMEDIATE(0, 4, 0)
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/* data processing */
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/* operations */
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#define and (0x0 << 21)
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#define eor (0x1 << 21)
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#define sub (0x2 << 21)
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#define rsb (0x3 << 21)
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#define add (0x4 << 21)
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#define adc (0x5 << 21)
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#define sbc (0x6 << 21)
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#define rsc (0x7 << 21)
|
||||
#define tst (0x8 << 21)
|
||||
#define teq (0x9 << 21)
|
||||
#define cmp (0xa << 21)
|
||||
#define cmn (0xb << 21)
|
||||
#define orr (0xc << 21)
|
||||
#define mov (0xd << 21)
|
||||
#define bic (0xe << 21)
|
||||
#define mvn (0xf << 21)
|
||||
#define and 0x0
|
||||
#define eor 0x1
|
||||
#define sub 0x2
|
||||
#define rsb 0x3
|
||||
#define add 0x4
|
||||
#define adc 0x5
|
||||
#define sbc 0x6
|
||||
#define rsc 0x7
|
||||
#define tst 0x8
|
||||
#define teq 0x9
|
||||
#define cmp 0xa
|
||||
#define cmn 0xb
|
||||
#define orr 0xc
|
||||
#define mov 0xd
|
||||
#define bic 0xe
|
||||
#define mvn 0xf
|
||||
|
||||
#define OPDP(cond, op) (cond | op)
|
||||
#define OPDP(cond, op) ((cond << 28) | (op << 21))
|
||||
#define OPDPF (32 << AOD_SIZE)
|
||||
#define OPDPI(cond, op) (cond | op | (0x1 << 25))
|
||||
#define OPDPI(cond, op) ((cond << 28) | (op << 21) | (0x1 << 25))
|
||||
#define OPDPIF (32 << AOD_SIZE)
|
||||
#define OPDPI_U12 AO_IMMEDIATE(0, 12, 0)
|
||||
#define OPDPS(cond, op) (cond | op | (0x1 << 20))
|
||||
#define OPDPS(cond, op) ((cond << 28) | (op << 21) | (0x1 << 20))
|
||||
#define OPDPSF (32 << AOD_SIZE)
|
||||
#define OPDPIS(cond, op)(cond | op | (0x1 << 25) | (0x1 << 20))
|
||||
#define OPDPIS(cond, op)((cond << 28) | (op << 21) | (0x1 << 25) | (0x1 << 20))
|
||||
#define OPDPISF (32 << AOD_SIZE)
|
||||
#define OPDPIS_U12 OPDPI_U12
|
||||
|
||||
/* multiply and multiply-accumulate */
|
||||
#define OPMUL(cond) (cond | (0x9 << 4))
|
||||
#define OPMUL(cond) ((cond << 28) | (0x9 << 4))
|
||||
#define OPMULF (32 << AOD_SIZE)
|
||||
#define OPMULS(cond) (cond | (0x1 << 20) | (0x9 << 4))
|
||||
#define OPMULS(cond) ((cond << 28) | (0x1 << 20) | (0x9 << 4))
|
||||
#define OPMULSF (32 << AOD_SIZE)
|
||||
#define OPMULA(cond) (cond | (0x1 << 21) | (0x9 << 4))
|
||||
#define OPMULA(cond) ((cond << 28) | (0x1 << 21) | (0x9 << 4))
|
||||
#define OPMULAF (32 << AOD_SIZE)
|
||||
#define OPMULAS(cond) (cond | (0x1 << 21) | (0x1 << 20) | (0x9 << 4))
|
||||
#define OPMULAS(cond) ((cond << 28) | (0x1 << 21) | (0x1 << 20) | (0x9 << 4))
|
||||
#define OPMULASF (32 << AOD_SIZE)
|
||||
|
||||
/* psr transfer */
|
||||
#define OPPT(cond) (cond | (0x2 << 23) | (0xf << 16))
|
||||
#define OPPT(cond) ((cond << 28) | (0x2 << 23) | (0xf << 16))
|
||||
#define OPPTF (32 << AOD_SIZE)
|
||||
#define OPPTI(cond) (cond | (0x2 << 23) | (0x29f << 12))
|
||||
#define OPPTI(cond) ((cond << 28) | (0x2 << 23) | (0x29f << 12))
|
||||
#define OPPTIF (32 << AOD_SIZE)
|
||||
|
||||
/* single data transfer */
|
||||
#define OPSDTL(cond) (cond | (0x1 << 26) | (0x1 << 25) | (0x1 << 20))
|
||||
#define OPSDTL(cond) ((cond << 28) | (0x1 << 26) | (0x1 << 25) | (0x1 << 20))
|
||||
#define OPSDTLF (32 << AOD_SIZE)
|
||||
#define OPSDTS(cond) (cond | (0x1 << 26) | (0x1 << 25))
|
||||
#define OPSDTS(cond) ((cond << 28) | (0x1 << 26) | (0x1 << 25))
|
||||
#define OPSDTSF (32 << AOD_SIZE)
|
||||
#define OPSDTLB(cond) (cond | (0x1 << 26) | (0x1 << 25) | (0x1 << 22) \
|
||||
| (0x1 << 20))
|
||||
#define OPSDTLB(cond) ((cond << 28) | (0x1 << 26) | (0x1 << 25) \
|
||||
| (0x1 << 22) | (0x1 << 20))
|
||||
#define OPSDTLBF (32 << AOD_SIZE)
|
||||
#define OPSDTSB(cond) (cond | (0x1 << 26) | (0x1 << 25) | (0x1 << 22))
|
||||
#define OPSDTSB(cond) ((cond << 28) | (0x1 << 26) | (0x1 << 25) | (0x1 << 22))
|
||||
#define OPSDTSBF (32 << AOD_SIZE)
|
||||
|
||||
/* single data swap */
|
||||
#define OPSDS(cond) (cond | (0x2 << 23) | (0x9 << 4))
|
||||
#define OPSDS(cond) ((cond << 28) | (0x2 << 23) | (0x9 << 4))
|
||||
#define OPSDSF (32 << AOD_SIZE)
|
||||
#define OPSDSB(cond) (cond | (0x2 << 23) | (0x1 << 22) | (0x9 << 4))
|
||||
#define OPSDSB(cond) ((cond << 28) | (0x2 << 23) | (0x1 << 22) | (0x9 << 4))
|
||||
#define OPSDSBF (32 << AOD_SIZE)
|
||||
|
||||
/* software interrupt */
|
||||
#define OPSI(cond) (cond | (0xf << 24))
|
||||
#define OPSI(cond) ((cond << 28) | (0xf << 24))
|
||||
#define OPSIF (32 << AOD_SIZE)
|
||||
#define OPSI_U24 AO_IMMEDIATE(0, 24, 0)
|
||||
|
||||
|
|
|
|||
|
|
@ -72,13 +72,13 @@ yasep32.o_ASFLAGS = $(CPPFLAGSF) $(CPPFLAGS) $(ASFLAGS) -a yasep32 -f flat
|
|||
amd64.o: amd64.asm ../src/asm
|
||||
$(AS) $(amd64.o_ASFLAGS) -o amd64.o amd64.asm
|
||||
|
||||
arm.o: arm.asm ../src/asm
|
||||
arm.o: arm.asm ../src/arch/arm.so ../src/asm
|
||||
$(AS) $(arm.o_ASFLAGS) -o arm.o arm.asm
|
||||
|
||||
armeb.o: armeb.asm arm.asm ../src/asm
|
||||
armeb.o: armeb.asm ../src/arch/armeb.so arm.asm ../src/asm
|
||||
$(AS) $(armeb.o_ASFLAGS) -o armeb.o armeb.asm
|
||||
|
||||
armel.o: armel.asm arm.asm ../src/asm
|
||||
armel.o: armel.asm ../src/arch/armel.so arm.asm ../src/asm
|
||||
$(AS) $(armel.o_ASFLAGS) -o armel.o armel.asm
|
||||
|
||||
dalvik.o: dalvik.asm ../src/asm
|
||||
|
|
|
|||
|
|
@ -2,8 +2,34 @@
|
|||
.text
|
||||
adc %r3, %r4, %r5
|
||||
adceq %r3, %r4, %r5
|
||||
adcne %r3, %r4, %r5
|
||||
adccs %r3, %r4, %r5
|
||||
adccc %r3, %r4, %r5
|
||||
adcmi %r3, %r4, %r5
|
||||
adcpl %r3, %r4, %r5
|
||||
adcvs %r3, %r4, %r5
|
||||
adcvc %r3, %r4, %r5
|
||||
adchi %r3, %r4, %r5
|
||||
adcls %r3, %r4, %r5
|
||||
adcge %r3, %r4, %r5
|
||||
adclt %r3, %r4, %r5
|
||||
adcgt %r3, %r4, %r5
|
||||
adcle %r3, %r4, %r5
|
||||
adcal %r3, %r4, %r5
|
||||
adc %r4, %r5, $0x0
|
||||
adceq %r4, %r5, $0x1
|
||||
adcne %r4, %r5, $0x2
|
||||
adccc %r4, %r5, $0x3
|
||||
adcpl %r4, %r5, $0x4
|
||||
adcvs %r4, %r5, $0x5
|
||||
adcvc %r4, %r5, $0x6
|
||||
adchi %r4, %r5, $0x7
|
||||
adcls %r4, %r5, $0x8
|
||||
adcge %r4, %r5, $0x9
|
||||
adclt %r4, %r5, $0xa
|
||||
adcgt %r4, %r5, $0xb
|
||||
adcle %r4, %r5, $0xc
|
||||
adcal %r4, %r5, $0xd
|
||||
adcs %r3, %r4, %r5
|
||||
adceqs %r3, %r4, %r5
|
||||
adcs %r3, %r4, $0x0
|
||||
|
|
@ -38,8 +64,8 @@
|
|||
bleq $0xa0
|
||||
bx %r1
|
||||
bxeq %r2
|
||||
cdp $0x1, $0xf, %r0
|
||||
cdpeq $0x2, $0xe, %r0
|
||||
cdp $0x1, $0xf, %r3
|
||||
cdpeq $0x2, $0xe, %r4
|
||||
cmn %r5, %r4
|
||||
cmneq %r5, %r4
|
||||
cmn %r5, $0x1
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@ sources=arm.asm
|
|||
|
||||
[arm.asm]
|
||||
asflags=-a arm
|
||||
depends=../src/asm
|
||||
depends=../src/arch/arm.so,../src/asm
|
||||
|
||||
[armeb.o]
|
||||
type=object
|
||||
|
|
@ -24,7 +24,7 @@ sources=armeb.asm
|
|||
|
||||
[armeb.asm]
|
||||
asflags=-a armeb
|
||||
depends=arm.asm,../src/asm
|
||||
depends=../src/arch/armeb.so,arm.asm,../src/asm
|
||||
|
||||
[armel.o]
|
||||
type=object
|
||||
|
|
@ -32,7 +32,7 @@ sources=armel.asm
|
|||
|
||||
[armel.asm]
|
||||
asflags=-a armel
|
||||
depends=arm.asm,../src/asm
|
||||
depends=../src/arch/armel.so,arm.asm,../src/asm
|
||||
|
||||
[dalvik.o]
|
||||
type=object
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user