Beginning to truly implement ARM support
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74130f88fe
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baa8076906
128
src/arch/arm.ins
128
src/arch/arm.ins
@ -18,10 +18,134 @@
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/* generic */
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/* registers */
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/* conditions */
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#define eq 0x0
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#define ne 0x1
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#define cs 0x2
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#define cc 0x3
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#define mi 0x4
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#define pl 0x5
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#define vs 0x6
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#define vc 0x7
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#define hi 0x8
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#define ls 0x9
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#define ge 0xa
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#define lt 0xb
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#define gt 0xc
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#define le 0xd
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#define al 0xe
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/* opcodes */
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#define OPNOP AO_IMMEDIATE(0, 32, 0)
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#define OPNOP AO_IMMEDIATE(0, 32, 0)
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#define OP_R AO_REGISTER(0, 32, 0)
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/* branch and exchange */
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#define OPBX(cond) (cond | 0x97ff9 << 4)
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/* data processing */
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#define OP_DATA2 AO_IMMEDIATE(0, 12, 0)
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/* instructions */
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/* FIXME verify */
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#if 1 /* FIXME really implement */
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{ "adc", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "add", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "and", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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/* b */
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{ "b", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "beq", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "bne", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "bcs", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "bcc", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "bmi", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "bpl", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "bvs", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "bvc", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "bhi", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "bls", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "bge", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "blt", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "bgt", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "bge", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "bal", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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/* bic */
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{ "bic", 0x00000000, OPNOP, OP_R, OP_R, OP_DATA2 },
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/* bl */
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{ "bl", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "bleq", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "blne", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "blcs", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "blcc", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "blmi", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "blpl", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "blvs", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "blvc", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "blhi", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "blls", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "blge", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "bllt", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "blgt", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "blge", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "blal", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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/* bx */
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{ "bx", OPBX(al), OPNOP, OP_R, AOT_NONE, AOT_NONE },
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{ "bxeq", OPBX(eq), OPNOP, OP_R, AOT_NONE, AOT_NONE },
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{ "bxne", OPBX(ne), OPNOP, OP_R, AOT_NONE, AOT_NONE },
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{ "bxcs", OPBX(cs), OPNOP, OP_R, AOT_NONE, AOT_NONE },
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{ "bxcc", OPBX(cc), OPNOP, OP_R, AOT_NONE, AOT_NONE },
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{ "bxmi", OPBX(mi), OPNOP, OP_R, AOT_NONE, AOT_NONE },
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{ "bxpl", OPBX(pl), OPNOP, OP_R, AOT_NONE, AOT_NONE },
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{ "bxvs", OPBX(vs), OPNOP, OP_R, AOT_NONE, AOT_NONE },
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{ "bxvc", OPBX(vc), OPNOP, OP_R, AOT_NONE, AOT_NONE },
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{ "bxhi", OPBX(hi), OPNOP, OP_R, AOT_NONE, AOT_NONE },
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{ "bxls", OPBX(ls), OPNOP, OP_R, AOT_NONE, AOT_NONE },
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{ "bxge", OPBX(ge), OPNOP, OP_R, AOT_NONE, AOT_NONE },
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{ "bxlt", OPBX(lt), OPNOP, OP_R, AOT_NONE, AOT_NONE },
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{ "bxgt", OPBX(gt), OPNOP, OP_R, AOT_NONE, AOT_NONE },
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{ "bxge", OPBX(ge), OPNOP, OP_R, AOT_NONE, AOT_NONE },
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{ "bxal", OPBX(al), OPNOP, OP_R, AOT_NONE, AOT_NONE },
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/* cdp */
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{ "cdp", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "cmn", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "cmp", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "eor", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "ldc", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "ldm", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "ldr", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "mla", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "mov", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "mrc", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "mrs", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE },
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/* msr */
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{ "msr", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE },
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{ "msreq", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE },
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{ "msrne", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE },
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{ "msrcs", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE },
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{ "msrcc", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE },
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{ "msrmi", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE },
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{ "msrpl", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE },
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{ "msrvs", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE },
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{ "msrvc", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE },
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{ "msrhi", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE },
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{ "msrls", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE },
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{ "msrge", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE },
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{ "msrlt", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE },
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{ "msrgt", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE },
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{ "msrle", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE },
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{ "msral", 0x00000000, OPNOP, OP_R, OP_R, AOT_NONE },
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{ "mul", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "mvn", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "nop", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "orr", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "rsb", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "rsc", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "sbc", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "stc", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "stm", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "str", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "sub", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "swi", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "swp", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "teq", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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{ "tst", 0x00000000, OPNOP, AOT_NONE, AOT_NONE, AOT_NONE },
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#endif
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@ -14,51 +14,8 @@ REG(r12, 32, 0x0c)
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REG(r13, 32, 0x0d)
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REG(r14, 32, 0x0e)
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REG(r15, 32, 0x0f)
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REG(r16, 32, 0x10)
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REG(r17, 32, 0x11)
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REG(r18, 32, 0x12)
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REG(r19, 32, 0x13)
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REG(r20, 32, 0x14)
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REG(r21, 32, 0x15)
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REG(r22, 32, 0x16)
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REG(r23, 32, 0x17)
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REG(r24, 32, 0x18)
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REG(r25, 32, 0x19)
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REG(r26, 32, 0x1a)
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REG(r27, 32, 0x1b)
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REG(r28, 32, 0x1c)
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REG(r29, 32, 0x1d)
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REG(r30, 32, 0x1e)
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REG(r31, 32, 0x1f)
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REG(f0, 32, 0x31)
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REG(f1, 32, 0x32)
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REG(f2, 32, 0x33)
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REG(f3, 32, 0x34)
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REG(f4, 32, 0x35)
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REG(f5, 32, 0x36)
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REG(f6, 32, 0x37)
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REG(f7, 32, 0x38)
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REG(f8, 32, 0x39)
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REG(f9, 32, 0x3a)
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REG(f10, 32, 0x3b)
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REG(f11, 32, 0x3c)
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REG(f12, 32, 0x3d)
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REG(f13, 32, 0x3e)
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REG(f14, 32, 0x3f)
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REG(f15, 32, 0x40)
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REG(f16, 32, 0x41)
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REG(f17, 32, 0x42)
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REG(f18, 32, 0x43)
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REG(f19, 32, 0x44)
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REG(f20, 32, 0x45)
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REG(f21, 32, 0x46)
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REG(f22, 32, 0x47)
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REG(f23, 32, 0x48)
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REG(f24, 32, 0x49)
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REG(f25, 32, 0x4a)
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REG(f26, 32, 0x4b)
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REG(f27, 32, 0x4c)
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REG(f28, 32, 0x4d)
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REG(f29, 32, 0x4e)
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REG(f30, 32, 0x4f)
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REG(f31, 32, 0x50)
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REG(sp, 32, 0x0d)
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REG(lr, 32, 0x0e)
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REG(pc, 32, 0x0f)
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REG(cpsr,32, 0x10)
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REG(spsr,32, 0x11)
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@ -1,2 +1,7 @@
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.text
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bx %r0
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bxeq %r0
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bic %r0, %r0, $0x1f
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mrs %r0, %cpsr
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msr %r0, %cpsr
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nop
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