Let the "verilog" test really be functional

2017-11-18 05:08:21 +01:00 · 2017-11-18 05:08:21 +01:00 · a0325a86b5
commit a0325a86b5
parent aaeccbeee4
2 changed files with 2 additions and 0 deletions
--- a/tests/verilog/Makefile.NetBSD
+++ b/tests/verilog/Makefile.NetBSD
@ -4,6 +4,7 @@ PREFIX	= /usr/local
 DESTDIR	=
 BINDIR	= $(PREFIX)/bin
 SBINDIR	= $(PREFIX)/sbin
+VERILOG	= iverilog
 EXEEXT	=
 RM	= rm -f
 LN	= ln -f
--- a/tests/verilog/project.conf
+++ b/tests/verilog/project.conf
@ -1,4 +1,5 @@
 targets=top.vhdl,top.vvp,top.fpga
+verilog=iverilog

 [top.fpga]
 type=object