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Let the "verilog" test really be functional

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This commit is contained in:
Pierre Pronchery 2017-11-18 05:08:21 +01:00
parent aaeccbeee4
commit a0325a86b5
2 changed files with 2 additions and 0 deletions
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1
tests/verilog/Makefile.NetBSD
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@ -4,6 +4,7 @@ PREFIX = /usr/local
DESTDIR = DESTDIR =
BINDIR = $(PREFIX)/bin BINDIR = $(PREFIX)/bin
SBINDIR = $(PREFIX)/sbin SBINDIR = $(PREFIX)/sbin
VERILOG = iverilog
EXEEXT = EXEEXT =
RM = rm -f RM = rm -f
LN = ln -f LN = ln -f

1
tests/verilog/project.conf
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@ -1,4 +1,5 @@
targets=top.vhdl,top.vvp,top.fpga targets=top.vhdl,top.vvp,top.fpga
verilog=iverilog
[top.fpga] [top.fpga]
type=object type=object