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It is really the 16-bit version of the Yasep processor

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This commit is contained in:
Pierre Pronchery 2011-11-28 03:32:16 +00:00
parent 6290fa7746
commit 75f5c2830f
2 changed files with 19 additions and 19 deletions
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6
src/arch/yasep.ins
View File

@ -27,11 +27,11 @@
#define OPIRLF (32 << AOD_SIZE)
#define OPRRLF (32 << AOD_SIZE)
/* operands */
#define OP_DST3 AO_REGISTER(0, 32, 0)
#define OP_DST3 AO_REGISTER(0, 16, 0)
#define OP_IMM4 AO_IMMEDIATE(0, 4, 0)
#define OP_IMM16 AO_IMMEDIATE(0, 16, 0)
#define OP_SI4 AO_REGISTER(0, 32, 0)
#define OP_SND AO_REGISTER(0, 32, 0)
#define OP_SI4 AO_REGISTER(0, 16, 0)
#define OP_SND AO_REGISTER(0, 16, 0)
/* instructions */
{ "add", OPIR(0x03), OPIRF, AO_2(OP_IMM4, OP_SND) },

32
src/arch/yasep.reg
View File

@ -1,16 +1,16 @@
REG(r0, 32, 0x00)
REG(r1, 32, 0x01)
REG(r2, 32, 0x02)
REG(r3, 32, 0x03)
REG(r4, 32, 0x04)
REG(r5, 32, 0x05)
REG(r6, 32, 0x06)
REG(r7, 32, 0x07)
REG(r8, 32, 0x08)
REG(r9, 32, 0x09)
REG(r10, 32, 0x0a)
REG(r11, 32, 0x0b)
REG(r12, 32, 0x0c)
REG(r13, 32, 0x0d)
REG(r14, 32, 0x0e)
REG(r15, 32, 0x0f)
REG(r0, 16, 0x00)
REG(r1, 16, 0x01)
REG(r2, 16, 0x02)
REG(r3, 16, 0x03)
REG(r4, 16, 0x04)
REG(r5, 16, 0x05)
REG(r6, 16, 0x06)
REG(r7, 16, 0x07)
REG(r8, 16, 0x08)
REG(r9, 16, 0x09)
REG(r10, 16, 0x0a)
REG(r11, 16, 0x0b)
REG(r12, 16, 0x0c)
REG(r13, 16, 0x0d)
REG(r14, 16, 0x0e)
REG(r15, 16, 0x0f)